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Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2011-01-10 12:39:04 +00:00
parent badbd2fde9
commit 16c29b5f28
108 changed files with 564 additions and 543 deletions
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8
include/llvm/CodeGen/MachineFrameInfo.h
View File

@ -27,7 +27,7 @@ class TargetRegisterClass;
class Type;
class MachineFunction;
class MachineBasicBlock;
class TargetFrameInfo;
class TargetFrameLowering;
class BitVector;
/// The CalleeSavedInfo class tracks the information need to locate where a
@ -196,9 +196,9 @@ class MachineFrameInfo {
/// spill slots.
SmallVector<bool, 8> SpillObjects;
/// TargetFrameInfo - Target information about frame layout.
/// TargetFrameLowering - Target information about frame layout.
///
const TargetFrameInfo &TFI;
const TargetFrameLowering &TFI;
/// LocalFrameObjects - References to frame indices which are mapped
/// into the local frame allocation block. <FrameIdx, LocalOffset>
@ -217,7 +217,7 @@ class MachineFrameInfo {
bool UseLocalStackAllocationBlock;
public:
explicit MachineFrameInfo(const TargetFrameInfo &tfi) : TFI(tfi) {
explicit MachineFrameInfo(const TargetFrameLowering &tfi) : TFI(tfi) {
StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
HasVarSizedObjects = false;
FrameAddressTaken = false;

6
include/llvm/Target/TargetAsmInfo.h
View File

@ -16,7 +16,7 @@
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
@ -28,7 +28,7 @@ namespace llvm {
class TargetAsmInfo {
unsigned PointerSize;
bool IsLittleEndian;
TargetFrameInfo::StackDirection StackDir;
TargetFrameLowering::StackDirection StackDir;
const TargetRegisterInfo *TRI;
std::vector<MachineMove> InitialFrameState;
const TargetLoweringObjectFile *TLOF;
@ -46,7 +46,7 @@ public:
return IsLittleEndian;
}
TargetFrameInfo::StackDirection getStackGrowthDirection() const {
TargetFrameLowering::StackDirection getStackGrowthDirection() const {
return StackDir;
}

14
include/llvm/Target/TargetFrameInfo.h → include/llvm/Target/TargetFrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===//
//===-- llvm/Target/TargetFrameLowering.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETFRAMEINFO_H
#define LLVM_TARGET_TARGETFRAMEINFO_H
#ifndef LLVM_TARGET_TARGETFRAMELOWERING_H
#define LLVM_TARGET_TARGETFRAMELOWERING_H
#include "llvm/CodeGen/MachineBasicBlock.h"
@ -33,7 +33,7 @@ namespace llvm {
/// The offset to the local area is the offset from the stack pointer on
/// function entry to the first location where function data (local variables,
/// spill locations) can be stored.
class TargetFrameInfo {
class TargetFrameLowering {
public:
enum StackDirection {
StackGrowsUp, // Adding to the stack increases the stack address
@ -51,12 +51,12 @@ private:
unsigned TransientStackAlignment;
int LocalAreaOffset;
public:
TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO,
unsigned TransAl = 1)
TargetFrameLowering(StackDirection D, unsigned StackAl, int LAO,
unsigned TransAl = 1)
: StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
LocalAreaOffset(LAO) {}
virtual ~TargetFrameInfo();
virtual ~TargetFrameLowering();
// These methods return information that describes the abstract stack layout
// of the target machine.

8
include/llvm/Target/TargetMachine.h
View File

@ -29,7 +29,7 @@ class TargetIntrinsicInfo;
class TargetJITInfo;
class TargetLowering;
class TargetSelectionDAGInfo;
class TargetFrameInfo;
class TargetFrameLowering;
class JITCodeEmitter;
class MCContext;
class TargetRegisterInfo;
@ -117,11 +117,11 @@ public:
// -- Stack frame information
// -- Selection DAG lowering information
//
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
virtual const TargetLowering *getTargetLowering() const { return 0; }
virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
virtual const TargetData *getTargetData() const { return 0; }
virtual const TargetData *getTargetData() const { return 0; }
/// getMCAsmInfo - Return target specific asm information.
///

6
lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
View File

@ -19,7 +19,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
@ -214,8 +214,8 @@ void AsmPrinter::EmitFrameMoves(const std::vector<MachineMove> &Moves,
const TargetRegisterInfo *RI = TM.getRegisterInfo();
int stackGrowth = TM.getTargetData()->getPointerSize();
if (TM.getFrameInfo()->getStackGrowthDirection() !=
TargetFrameInfo::StackGrowsUp)
if (TM.getFrameLowering()->getStackGrowthDirection() !=
TargetFrameLowering::StackGrowsUp)
stackGrowth *= -1;
for (unsigned i = 0, N = Moves.size(); i < N; ++i) {

10
lib/CodeGen/AsmPrinter/DwarfDebug.cpp
View File

@ -24,7 +24,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
@ -594,7 +594,7 @@ void DwarfDebug::addSourceLine(DIE *Die, DINameSpace NS) {
void DwarfDebug::addVariableAddress(DbgVariable *&DV, DIE *Die, int64_t FI) {
MachineLocation Location;
unsigned FrameReg;
const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
int Offset = TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
Location.set(FrameReg, Offset);
@ -3294,8 +3294,8 @@ void DwarfDebug::emitCommonDebugFrame() {
return;
int stackGrowth = Asm->getTargetData().getPointerSize();
if (Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsDown)
if (Asm->TM.getFrameLowering()->getStackGrowthDirection() ==
TargetFrameLowering::StackGrowsDown)
stackGrowth *= -1;
// Start the dwarf frame section.
@ -3318,7 +3318,7 @@ void DwarfDebug::emitCommonDebugFrame() {
Asm->EmitSLEB128(stackGrowth, "CIE Data Alignment Factor");
Asm->OutStreamer.AddComment("CIE RA Column");
const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false));
std::vector<MachineMove> Moves;

8
lib/CodeGen/AsmPrinter/DwarfException.cpp
View File

@ -26,7 +26,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@ -50,8 +50,8 @@ DwarfException::~DwarfException() {}
void DwarfException::EmitCIE(const Function *PersonalityFn, unsigned Index) {
// Size and sign of stack growth.
int stackGrowth = Asm->getTargetData().getPointerSize();
if (Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsDown)
if (Asm->TM.getFrameLowering()->getStackGrowthDirection() ==
TargetFrameLowering::StackGrowsDown)
stackGrowth *= -1;
const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering();
@ -127,7 +127,7 @@ void DwarfException::EmitCIE(const Function *PersonalityFn, unsigned Index) {
Asm->OutStreamer.AddComment("CIE Return Address Column");
const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
if (Augmentation[0]) {

4
lib/CodeGen/GCStrategy.cpp
View File

@ -24,7 +24,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
@ -382,7 +382,7 @@ void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {
}
void MachineCodeAnalysis::FindStackOffsets(MachineFunction &MF) {
const TargetFrameInfo *TFI = TM->getFrameInfo();
const TargetFrameLowering *TFI = TM->getFrameLowering();
assert(TFI && "TargetRegisterInfo not available!");
for (GCFunctionInfo::roots_iterator RI = FI->roots_begin(),

10
lib/CodeGen/LocalStackSlotAllocation.cpp
View File

@ -34,7 +34,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
using namespace llvm;
@ -152,9 +152,9 @@ void LocalStackSlotPass::AdjustStackOffset(MachineFrameInfo *MFI,
void LocalStackSlotPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
// Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *MFI = Fn.getFrameInfo();
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
int64_t Offset = 0;
unsigned MaxAlign = 0;
@ -227,9 +227,9 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
MachineFrameInfo *MFI = Fn.getFrameInfo();
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
// Collect all of the instructions in the block that reference
// a frame index. Also store the frame index referenced to ease later

6
lib/CodeGen/MachineFunction.cpp
View File

@ -33,7 +33,7 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/GraphWriter.h"
@ -60,7 +60,7 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
else
RegInfo = 0;
MFInfo = 0;
FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameInfo());
FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameLowering());
if (Fn->hasFnAttr(Attribute::StackAlignment))
FrameInfo->setMaxAlignment(Attribute::getStackAlignmentFromAttrs(
Fn->getAttributes().getFnAttributes()));
@ -492,7 +492,7 @@ MachineFrameInfo::getPristineRegs(const MachineBasicBlock *MBB) const {
void MachineFrameInfo::print(const MachineFunction &MF, raw_ostream &OS) const{
if (Objects.empty()) return;
const TargetFrameInfo *FI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *FI = MF.getTarget().getFrameLowering();
int ValOffset = (FI ? FI->getOffsetOfLocalArea() : 0);
OS << "Frame Objects:\n";

24
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -30,7 +30,7 @@
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
@ -66,7 +66,7 @@ FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); }
bool PEI::runOnMachineFunction(MachineFunction &Fn) {
const Function* F = Fn.getFunction();
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
@ -145,7 +145,7 @@ void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
/// pseudo instructions.
void PEI::calculateCallsInformation(MachineFunction &Fn) {
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
MachineFrameInfo *MFI = Fn.getFrameInfo();
unsigned MaxCallFrameSize = 0;
@ -199,7 +199,7 @@ void PEI::calculateCallsInformation(MachineFunction &Fn) {
/// registers.
void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
MachineFrameInfo *MFI = Fn.getFrameInfo();
// Get the callee saved register list...
@ -238,7 +238,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
return; // Early exit if no callee saved registers are modified!
unsigned NumFixedSpillSlots;
const TargetFrameInfo::SpillSlot *FixedSpillSlots =
const TargetFrameLowering::SpillSlot *FixedSpillSlots =
TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots);
// Now that we know which registers need to be saved and restored, allocate
@ -256,7 +256,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
// Check to see if this physreg must be spilled to a particular stack slot
// on this target.
const TargetFrameInfo::SpillSlot *FixedSlot = FixedSpillSlots;
const TargetFrameLowering::SpillSlot *FixedSlot = FixedSpillSlots;
while (FixedSlot != FixedSpillSlots+NumFixedSpillSlots &&
FixedSlot->Reg != Reg)
++FixedSlot;
@ -299,7 +299,7 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
return;
const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
MachineBasicBlock::iterator I;
@ -490,10 +490,10 @@ AdjustStackOffset(MachineFrameInfo *MFI, int FrameIdx,
/// abstract stack objects.
///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
// Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *MFI = Fn.getFrameInfo();
@ -682,7 +682,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
/// prolog and epilog code to the function.
///
void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
// Add prologue to the function...
TFI.emitPrologue(Fn);
@ -704,9 +704,9 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
bool StackGrowsDown =
TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();

1
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -25,7 +25,6 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"

1
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -29,7 +29,6 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"

4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -19,7 +19,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
@ -1719,7 +1719,7 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
if (Align > StackAlign)
SP = DAG.getNode(ISD::AND, dl, VT, SP,
DAG.getConstant(-(uint64_t)Align, VT));

1
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -31,7 +31,6 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSelectionDAGInfo.h"
#include "llvm/Target/TargetOptions.h"

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -45,7 +45,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
@ -2974,7 +2974,7 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
// Handle alignment. If the requested alignment is less than or equal to
// the stack alignment, ignore it. If the size is greater than or equal to
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
if (Align <= StackAlign)
Align = 0;

10
lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
View File

@ -26,7 +26,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
@ -43,9 +43,9 @@ unsigned char* JITDwarfEmitter::EmitDwarfTable(MachineFunction& F,
const TargetMachine& TM = F.getTarget();
TD = TM.getTargetData();
stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection();
stackGrowthDirection = TM.getFrameLowering()->getStackGrowthDirection();
RI = TM.getRegisterInfo();
TFI = TM.getFrameInfo();
TFI = TM.getFrameLowering();
JCE = &jce;
unsigned char* ExceptionTable = EmitExceptionTable(&F, StartFunction,
@ -67,7 +67,7 @@ void
JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
const std::vector<MachineMove> &Moves) const {
unsigned PointerSize = TD->getPointerSize();
int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ?
PointerSize : -PointerSize;
MCSymbol *BaseLabel = 0;
@ -482,7 +482,7 @@ unsigned char* JITDwarfEmitter::EmitExceptionTable(MachineFunction* MF,
unsigned char*
JITDwarfEmitter::EmitCommonEHFrame(const Function* Personality) const {
unsigned PointerSize = TD->getPointerSize();
int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ?
PointerSize : -PointerSize;
unsigned char* StartCommonPtr = (unsigned char*)JCE->getCurrentPCValue();

4
lib/ExecutionEngine/JIT/JITDwarfEmitter.h
View File

@ -23,7 +23,7 @@ class MachineFunction;
class MachineModuleInfo;
class MachineMove;
class TargetData;
class TargetFrameInfo;
class TargetFrameLowering;
class TargetMachine;
class TargetRegisterInfo;
@ -31,7 +31,7 @@ class JITDwarfEmitter {
const TargetData* TD;
JITCodeEmitter* JCE;
const TargetRegisterInfo* RI;
const TargetFrameInfo *TFI;
const TargetFrameLowering *TFI;
MachineModuleInfo* MMI;
JIT& Jit;
bool stackGrowthDirection;

2
lib/MC/MCDwarf.cpp
View File

@ -433,7 +433,7 @@ static int getDataAlignmentFactor(MCStreamer &streamer) {
MCContext &context = streamer.getContext();
const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
int size = asmInfo.getPointerSize();
if (asmInfo.getStackGrowthDirection() == TargetFrameInfo::StackGrowsUp)
if (asmInfo.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp)
return size;
else
return -size;

26
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -15,7 +15,7 @@
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMFrameInfo.h"
#include "ARMFrameLowering.h"
#include "ARMInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
@ -33,7 +33,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
@ -86,7 +86,7 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector ARMBaseRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
// FIXME: avoid re-calculating this everytime.
BitVector Reserved(getNumRegs());
@ -105,7 +105,7 @@ getReservedRegs(const MachineFunction &MF) const {
bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
unsigned Reg) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
switch (Reg) {
default: break;
@ -354,7 +354,7 @@ std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
unsigned HintType, unsigned HintReg,
const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
// Alternative register allocation orders when favoring even / odd registers
// of register pairs.
@ -575,7 +575,7 @@ bool ARMBaseRegisterInfo::
needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
F->hasFnAttr(Attribute::StackAlignment));
@ -597,7 +597,7 @@ unsigned ARMBaseRegisterInfo::getRARegister() const {
unsigned
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (TFI->hasFP(MF))
return FramePtr;
@ -852,7 +852,7 @@ emitSPUpdate(bool isARM,
void ARMBaseRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!TFI->hasReservedCallFrame(MF)) {
// If we have alloca, convert as follows:
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
@ -864,7 +864,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = TFI->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@ -984,7 +984,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
// Note that the incoming offset is based on the SP value at function entry,
// so it'll be negative.
MachineFunction &MF = *MI->getParent()->getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@ -1011,7 +1011,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
// The FP is only available if there is no dynamic realignment. We
// don't know for sure yet whether we'll need that, so we guess based
// on whether there are any local variables that would trigger it.
unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned StackAlign = TFI->getStackAlignment();
if (TFI->hasFP(MF) &&
!((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
if (isFrameOffsetLegal(MI, FPOffset))
@ -1155,8 +1155,8 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const ARMFrameInfo *TFI =
static_cast<const ARMFrameInfo*>(MF.getTarget().getFrameInfo());
const ARMFrameLowering *TFI =
static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert(!AFI->isThumb1OnlyFunction() &&
"This eliminateFrameIndex does not support Thumb1!");

4
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -24,7 +24,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
using namespace llvm;
@ -639,7 +639,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
int32_t NumBytes = AFI->getFramePtrSpillOffset();
unsigned FramePtr = RI.getFrameRegister(MF);
assert(MF.getTarget().getFrameInfo()->hasFP(MF) &&
assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
"base pointer without frame pointer?");
if (AFI->isThumb2Function()) {

36
lib/Target/ARM/ARMFrameInfo.cpp → lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the ARM implementation of TargetFrameInfo class.
// This file contains the ARM implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "ARMFrameInfo.h"
#include "ARMFrameLowering.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
@ -28,7 +28,7 @@ using namespace llvm;
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
///
bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
// Mac OS X requires FP not to be clobbered for backtracing purpose.
@ -48,7 +48,7 @@ bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
// immediately on entry to the current function. This eliminates the need for
// add/sub sp brackets around call sites. Returns true if the call frame is
// included as part of the stack frame.
bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
// It's not always a good idea to include the call frame as part of the
@ -65,7 +65,7 @@ bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
// call frame pseudos can be simplified. Unlike most targets, having a FP
// is not sufficient here since we still may reference some objects via SP
// even when FP is available in Thumb2 mode.
bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
}
@ -115,7 +115,7 @@ emitSPUpdate(bool isARM,
Pred, PredReg, TII);
}
void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -293,7 +293,7 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
AFI->setShouldRestoreSPFromFP(true);
}
void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getDesc().isReturn() &&
@ -418,13 +418,13 @@ void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
// FIXME: This can go wrong when references are SP-relative and simple call
// frames aren't used.
int
ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const {
return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
}
int
ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF,
ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
int FI,
unsigned &FrameReg,
int SPAdj) const {
@ -499,12 +499,12 @@ ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF,
return Offset;
}
int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
unsigned FrameReg;
return getFrameIndexReference(MF, FI, FrameReg);
}
void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
unsigned StmOpc, unsigned StrOpc, bool NoGap,
@ -572,7 +572,7 @@ void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
}
}
void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
unsigned LdmOpc, unsigned LdrOpc,
@ -642,7 +642,7 @@ void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
}
}
bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -663,7 +663,7 @@ bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -726,7 +726,7 @@ static unsigned estimateStackSize(MachineFunction &MF) {
/// instructions will require a scratch register during their expansion later.
// FIXME: Move to TII?
static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
const TargetFrameInfo *TFI) {
const TargetFrameLowering *TFI) {
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned Limit = (1 << 12) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
@ -775,7 +775,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
}
void
ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
// This tells PEI to spill the FP as if it is any other callee-save register
// to take advantage the eliminateFrameIndex machinery. This also ensures it
@ -933,7 +933,7 @@ ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// If stack and double are 8-byte aligned and we are spilling an odd number
// of GPRs, spill one extra callee save GPR so we won't have to pad between
// the integer and double callee save areas.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = getStackAlignment();
if (TargetAlign == 8 && (NumGPRSpills & 1)) {
if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {

11
lib/Target/ARM/ARMFrameInfo.h → lib/Target/ARM/ARMFrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- ARMTargetFrameInfo.h - Define TargetFrameInfo for ARM ---*- C++ -*-===//
//==-- ARMTargetFrameLowering.h - Define frame lowering for ARM --*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,19 @@
#include "ARM.h"
#include "ARMSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class ARMSubtarget;
class ARMFrameInfo : public TargetFrameInfo {
class ARMFrameLowering : public TargetFrameLowering {
protected:
const ARMSubtarget &STI;
public:
explicit ARMFrameInfo(const ARMSubtarget &sti)
: TargetFrameInfo(StackGrowsDown, sti.getStackAlignment(), 0, 4), STI(sti) {
explicit ARMFrameLowering(const ARMSubtarget &sti)
: TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -902,10 +902,11 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
return Sched::RegPressure;
}
// FIXME: Move to RegInfo
unsigned
ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
switch (RC->getID()) {
default:
@ -2317,7 +2318,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
unsigned NumGPRs = CCInfo.getFirstUnallocated
(GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
unsigned VARegSize = (4 - NumGPRs) * 4;
unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
unsigned ArgOffset = CCInfo.getNextStackOffset();

1
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -28,7 +28,6 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"

10
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -12,7 +12,7 @@
#include "ARMTargetMachine.h"
#include "ARMMCAsmInfo.h"
#include "ARMFrameInfo.h"
#include "ARMFrameLowering.h"
#include "ARM.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/Passes.h"
@ -102,7 +102,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
ELFWriterInfo(*this),
TLInfo(*this),
TSInfo(*this),
FrameInfo(Subtarget) {
FrameLowering(Subtarget) {
if (!Subtarget.hasARMOps())
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
"support ARM mode execution!");
@ -124,9 +124,9 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
ELFWriterInfo(*this),
TLInfo(*this),
TSInfo(*this),
FrameInfo(Subtarget.hasThumb2()
? new ARMFrameInfo(Subtarget)
: (ARMFrameInfo*)new Thumb1FrameInfo(Subtarget)) {
FrameLowering(Subtarget.hasThumb2()
? new ARMFrameLowering(Subtarget)
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
}
// Pass Pipeline Configuration

20
lib/Target/ARM/ARMTargetMachine.h
View File

@ -16,13 +16,13 @@
#include "ARMInstrInfo.h"
#include "ARMELFWriterInfo.h"
#include "ARMFrameInfo.h"
#include "ARMFrameLowering.h"
#include "ARMJITInfo.h"
#include "ARMSubtarget.h"
#include "ARMISelLowering.h"
#include "ARMSelectionDAGInfo.h"
#include "Thumb1InstrInfo.h"
#include "Thumb1FrameInfo.h"
#include "Thumb1FrameLowering.h"
#include "Thumb2InstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
@ -67,7 +67,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
ARMELFWriterInfo ELFWriterInfo;
ARMTargetLowering TLInfo;
ARMSelectionDAGInfo TSInfo;
ARMFrameInfo FrameInfo;
ARMFrameLowering FrameLowering;
public:
ARMTargetMachine(const Target &T, const std::string &TT,
const std::string &FS);
@ -83,7 +83,9 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
return &TSInfo;
}
virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const ARMFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetData *getTargetData() const { return &DataLayout; }
@ -103,8 +105,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine {
ARMELFWriterInfo ELFWriterInfo;
ARMTargetLowering TLInfo;
ARMSelectionDAGInfo TSInfo;
// Either Thumb1FrameInfo or ARMFrameInfo.
OwningPtr<ARMFrameInfo> FrameInfo;
// Either Thumb1FrameLowering or ARMFrameLowering.
OwningPtr<ARMFrameLowering> FrameLowering;
public:
ThumbTargetMachine(const Target &T, const std::string &TT,
const std::string &FS);
@ -126,9 +128,9 @@ public:
virtual const ARMBaseInstrInfo *getInstrInfo() const {
return InstrInfo.get();
}
/// returns either Thumb1FrameInfo or ARMFrameInfo
virtual const ARMFrameInfo *getFrameInfo() const {
return FrameInfo.get();
/// returns either Thumb1FrameLowering or ARMFrameLowering
virtual const ARMFrameLowering *getFrameLowering() const {
return FrameLowering.get();
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const ARMELFWriterInfo *getELFWriterInfo() const {

16
lib/Target/ARM/Thumb1FrameInfo.cpp → lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- Thumb1FrameInfo.cpp - Thumb1 Frame Information ------*- C++ -*-====//
//======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Thumb1 implementation of TargetFrameInfo class.
// This file contains the Thumb1 implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "Thumb1FrameInfo.h"
#include "Thumb1FrameLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@ -21,7 +21,7 @@
using namespace llvm;
bool Thumb1FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
// It's not always a good idea to include the call frame as part of the
@ -43,7 +43,7 @@ static void emitSPUpdate(MachineBasicBlock &MBB,
MRI, dl);
}
void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const {
void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -181,7 +181,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
return false;
}
void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF,
void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert((MBBI->getOpcode() == ARM::tBX_RET ||
@ -265,7 +265,7 @@ void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF,
}
}
bool Thumb1FrameInfo::
bool Thumb1FrameLowering::
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
@ -303,7 +303,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
bool Thumb1FrameInfo::
bool Thumb1FrameLowering::
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,

12
lib/Target/ARM/Thumb1FrameInfo.h → lib/Target/ARM/Thumb1FrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- Thumb1FrameInfo.h - Thumb1-specific frame info stuff ----*- C++ -*-===//
//===-- Thumb1FrameLowering.h - Thumb1-specific frame info stuff --*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -15,19 +15,19 @@
#define __THUMM_FRAMEINFO_H_
#include "ARM.h"
#include "ARMFrameInfo.h"
#include "ARMFrameLowering.h"
#include "ARMSubtarget.h"
#include "Thumb1InstrInfo.h"
#include "Thumb1RegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class ARMSubtarget;
class Thumb1FrameInfo : public ARMFrameInfo {
class Thumb1FrameLowering : public ARMFrameLowering {
public:
explicit Thumb1FrameInfo(const ARMSubtarget &sti)
: ARMFrameInfo(sti) {
explicit Thumb1FrameLowering(const ARMSubtarget &sti)
: ARMFrameLowering(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

8
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -29,7 +29,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
@ -290,7 +290,7 @@ static void emitSPUpdate(MachineBasicBlock &MBB,
void Thumb1RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!TFI->hasReservedCallFrame(MF)) {
// If we have alloca, convert as follows:
@ -303,7 +303,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = TFI->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
// Replace the pseudo instruction with a new instruction...
@ -602,7 +602,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
Offset -= AFI->getGPRCalleeSavedArea2Offset();
else if (MF.getFrameInfo()->hasVarSizedObjects()) {
assert(SPAdj == 0 && MF.getTarget().getFrameInfo()->hasFP(MF) &&
assert(SPAdj == 0 && MF.getTarget().getFrameLowering()->hasFP(MF) &&
"Unexpected");
// There are alloca()'s in this function, must reference off the frame
// pointer or base pointer instead.

1
lib/Target/ARM/Thumb2RegisterInfo.cpp
View File

@ -29,7 +29,6 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"

12
lib/Target/Alpha/AlphaFrameInfo.cpp → lib/Target/Alpha/AlphaFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=====- AlphaFrameInfo.cpp - Alpha Frame Information ----------*- C++ -*-====//
//=====- AlphaFrameLowering.cpp - Alpha Frame Information ------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Alpha implementation of TargetFrameInfo class.
// This file contains the Alpha implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "AlphaFrameInfo.h"
#include "AlphaFrameLowering.h"
#include "AlphaInstrInfo.h"
#include "AlphaMachineFunctionInfo.h"
#include "llvm/Function.h"
@ -38,12 +38,12 @@ static long getLower16(long l) {
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
bool AlphaFrameInfo::hasFP(const MachineFunction &MF) const {
bool AlphaFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->hasVarSizedObjects();
}
void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const {
void AlphaFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -101,7 +101,7 @@ void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const {
}
void AlphaFrameInfo::emitEpilogue(MachineFunction &MF,
void AlphaFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());

10
lib/Target/Alpha/AlphaFrameInfo.h → lib/Target/Alpha/AlphaFrameLowering.h
View File

@ -1,4 +1,4 @@
//===--- AlphaFrameInfo.h - Define TargetFrameInfo for Alpha --*- C++ -*---===//
//==-- AlphaFrameLowering.h - Define frame lowering for Alpha --*- C++ -*---==//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "Alpha.h"
#include "AlphaSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class AlphaSubtarget;
class AlphaFrameInfo : public TargetFrameInfo {
class AlphaFrameLowering : public TargetFrameLowering {
const AlphaSubtarget &STI;
// FIXME: This should end in MachineFunctionInfo, not here!
mutable int curgpdist;
public:
explicit AlphaFrameInfo(const AlphaSubtarget &sti)
: TargetFrameInfo(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) {
explicit AlphaFrameLowering(const AlphaSubtarget &sti)
: TargetFrameLowering(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

10
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -22,7 +22,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -81,7 +81,7 @@ BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
void AlphaRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (TFI->hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
@ -93,7 +93,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = TFI->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
MachineInstr *New;
@ -131,7 +131,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
bool FP = TFI->hasFP(MF);
@ -178,7 +178,7 @@ unsigned AlphaRegisterInfo::getRARegister() const {
}
unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
}

2
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -28,7 +28,7 @@ AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
const std::string &FS)
: LLVMTargetMachine(T, TT),
DataLayout("e-f128:128:128-n64"),
FrameInfo(Subtarget),
FrameLowering(Subtarget),
Subtarget(TT, FS),
TLInfo(*this),
TSInfo(*this) {

10
lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -16,12 +16,12 @@
#include "AlphaInstrInfo.h"
#include "AlphaISelLowering.h"
#include "AlphaFrameInfo.h"
#include "AlphaFrameLowering.h"
#include "AlphaSelectionDAGInfo.h"
#include "AlphaSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
@ -30,7 +30,7 @@ class GlobalValue;
class AlphaTargetMachine : public LLVMTargetMachine {
const TargetData DataLayout; // Calculates type size & alignment
AlphaInstrInfo InstrInfo;
AlphaFrameInfo FrameInfo;
AlphaFrameLowering FrameLowering;
AlphaSubtarget Subtarget;
AlphaTargetLowering TLInfo;
AlphaSelectionDAGInfo TSInfo;
@ -40,7 +40,9 @@ public:
const std::string &FS);
virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const AlphaSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual const AlphaRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();

14
lib/Target/Blackfin/BlackfinFrameInfo.cpp → lib/Target/Blackfin/BlackfinFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//====- BlackfinFrameInfo.cpp - Blackfin Frame Information ------*- C++ -*-===//
//====- BlackfinFrameLowering.cpp - Blackfin Frame Information --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Blackfin implementation of TargetFrameInfo class.
// This file contains the Blackfin implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "BlackfinFrameInfo.h"
#include "BlackfinFrameLowering.h"
#include "BlackfinInstrInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@ -25,7 +25,7 @@ using namespace llvm;
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool BlackfinFrameInfo::hasFP(const MachineFunction &MF) const {
bool BlackfinFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return DisableFramePointerElim(MF) ||
MFI->adjustsStack() || MFI->hasVarSizedObjects();
@ -34,7 +34,7 @@ bool BlackfinFrameInfo::hasFP(const MachineFunction &MF) const {
// Emit a prologue that sets up a stack frame.
// On function entry, R0-R2 and P0 may hold arguments.
// R3, P1, and P2 may be used as scratch registers
void BlackfinFrameInfo::emitPrologue(MachineFunction &MF) const {
void BlackfinFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -83,7 +83,7 @@ void BlackfinFrameInfo::emitPrologue(MachineFunction &MF) const {
}
void BlackfinFrameInfo::emitEpilogue(MachineFunction &MF,
void BlackfinFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
const BlackfinRegisterInfo *RegInfo =
@ -107,7 +107,7 @@ void BlackfinFrameInfo::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
}
void BlackfinFrameInfo::
void BlackfinFrameLowering::
processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
MachineFrameInfo *MFI = MF.getFrameInfo();

10
lib/Target/Blackfin/BlackfinFrameInfo.h → lib/Target/Blackfin/BlackfinFrameLowering.h
View File

@ -1,4 +1,4 @@
//=- BlackfinFrameInfo.h - Define TargetFrameInfo for Blackfin --*- C++ -*--==//
//=- BlackfinFrameLowering.h - Define frame lowering for Blackfin -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "Blackfin.h"
#include "BlackfinSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class BlackfinSubtarget;
class BlackfinFrameInfo : public TargetFrameInfo {
class BlackfinFrameLowering : public TargetFrameLowering {
protected:
const BlackfinSubtarget &STI;
public:
explicit BlackfinFrameInfo(const BlackfinSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), STI(sti) {
explicit BlackfinFrameLowering(const BlackfinSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

10
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -22,7 +22,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -50,7 +50,7 @@ BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector
BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
using namespace BF;
BitVector Reserved(getNumRegs());
@ -154,7 +154,7 @@ void BlackfinRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!TFI->hasReservedCallFrame(MF)) {
int64_t Amount = I->getOperand(0).getImm();
@ -191,7 +191,7 @@ BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
DebugLoc DL = MI.getDebugLoc();
unsigned FIPos;
@ -331,7 +331,7 @@ unsigned BlackfinRegisterInfo::getRARegister() const {
unsigned
BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? BF::FP : BF::SP;
}

10
lib/Target/Blackfin/BlackfinRegisterInfo.td
View File

@ -252,7 +252,7 @@ def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> {
PClass::iterator
PClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
return allocation_order_begin(MF)
+ (TFI->hasFP(MF) ? 7 : 6);
}
@ -275,7 +275,7 @@ def DP : RegisterClass<"BF", [i32], 32,
DPClass::iterator
DPClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
return allocation_order_begin(MF)
+ (TFI->hasFP(MF) ? 15 : 14);
}
@ -295,7 +295,7 @@ def GR : RegisterClass<"BF", [i32], 32,
GRClass::iterator
GRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
return allocation_order_begin(MF)
+ (TFI->hasFP(MF) ? 31 : 30);
}
@ -318,7 +318,7 @@ def ALL : RegisterClass<"BF", [i32], 32,
ALLClass::iterator
ALLClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
return allocation_order_begin(MF)
+ (TFI->hasFP(MF) ? 31 : 30);
}
@ -334,7 +334,7 @@ def PI : RegisterClass<"BF", [i32], 32,
PIClass::iterator
PIClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
return allocation_order_begin(MF)
+ (TFI->hasFP(MF) ? 11 : 10);
}

2
lib/Target/Blackfin/BlackfinTargetMachine.cpp
View File

@ -33,7 +33,7 @@ BlackfinTargetMachine::BlackfinTargetMachine(const Target &T,
TLInfo(*this),
TSInfo(*this),
InstrInfo(Subtarget),
FrameInfo(Subtarget) {
FrameLowering(Subtarget) {
}
bool BlackfinTargetMachine::addInstSelector(PassManagerBase &PM,

10
lib/Target/Blackfin/BlackfinTargetMachine.h
View File

@ -17,12 +17,12 @@
#include "BlackfinInstrInfo.h"
#include "BlackfinIntrinsicInfo.h"
#include "BlackfinISelLowering.h"
#include "BlackfinFrameInfo.h"
#include "BlackfinFrameLowering.h"
#include "BlackfinSubtarget.h"
#include "BlackfinSelectionDAGInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
@ -32,14 +32,16 @@ namespace llvm {
BlackfinTargetLowering TLInfo;
BlackfinSelectionDAGInfo TSInfo;
BlackfinInstrInfo InstrInfo;
BlackfinFrameInfo FrameInfo;
BlackfinFrameLowering FrameLowering;
BlackfinIntrinsicInfo IntrinsicInfo;
public:
BlackfinTargetMachine(const Target &T, const std::string &TT,
const std::string &FS);
virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const BlackfinSubtarget *getSubtargetImpl() const {
return &Subtarget;
}

31
lib/Target/CellSPU/SPUFrameInfo.cpp → lib/Target/CellSPU/SPUFrameLowering.cpp
View File

@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
#include "SPU.h"
#include "SPUFrameInfo.h"
#include "SPUFrameLowering.h"
#include "SPURegisterNames.h"
#include "SPUInstrBuilder.h"
#include "SPUInstrInfo.h"
@ -29,11 +29,11 @@
using namespace llvm;
//===----------------------------------------------------------------------===//
// SPUFrameInfo:
// SPUFrameLowering:
//===----------------------------------------------------------------------===//
SPUFrameInfo::SPUFrameInfo(const SPUSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
SPUFrameLowering::SPUFrameLowering(const SPUSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0),
Subtarget(sti) {
LR[0].first = SPU::R0;
LR[0].second = 16;
@ -44,7 +44,7 @@ SPUFrameInfo::SPUFrameInfo(const SPUSubtarget &sti)
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and has
// a non-zero stack size.
bool SPUFrameInfo::hasFP(const MachineFunction &MF) const {
bool SPUFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->getStackSize() &&
@ -54,7 +54,7 @@ bool SPUFrameInfo::hasFP(const MachineFunction &MF) const {
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.
void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const {
void SPUFrameLowering::determineFrameLayout(MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
// Get the number of bytes to allocate from the FrameInfo
@ -62,7 +62,7 @@ void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const {
// Get the alignments provided by the target, and the maximum alignment
// (if any) of the fixed frame objects.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = getStackAlignment();
unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
unsigned AlignMask = Align - 1;
@ -88,7 +88,7 @@ void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const {
MFI->setStackSize(FrameSize);
}
void SPUFrameInfo::emitPrologue(MachineFunction &MF) const {
void SPUFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -113,7 +113,7 @@ void SPUFrameInfo::emitPrologue(MachineFunction &MF) const {
// the "empty" frame size is 16 - just the register scavenger spill slot
if (FrameSize > 16 || MFI->adjustsStack()) {
FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
FrameSize = -(FrameSize + SPUFrameLowering::minStackSize());
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabel = MMI.getContext().CreateTempSymbol();
@ -186,7 +186,7 @@ void SPUFrameInfo::emitPrologue(MachineFunction &MF) const {
// This is a leaf function -- insert a branch hint iff there are
// sufficient number instructions in the basic block. Note that
// this is just a best guess based on the basic block's size.
if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
if (MBB.size() >= (unsigned) SPUFrameLowering::branchHintPenalty()) {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
dl = MBBI->getDebugLoc();
@ -197,14 +197,14 @@ void SPUFrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void SPUFrameInfo::emitEpilogue(MachineFunction &MF,
void SPUFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
const SPUInstrInfo &TII =
*static_cast<const SPUInstrInfo*>(MF.getTarget().getInstrInfo());
const MachineFrameInfo *MFI = MF.getFrameInfo();
int FrameSize = MFI->getStackSize();
int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
int LinkSlotOffset = SPUFrameLowering::stackSlotSize();
DebugLoc dl = MBBI->getDebugLoc();
assert(MBBI->getOpcode() == SPU::RET &&
@ -213,7 +213,7 @@ void SPUFrameInfo::emitEpilogue(MachineFunction &MF,
// the "empty" frame size is 16 - just the register scavenger spill slot
if (FrameSize > 16 || MFI->adjustsStack()) {
FrameSize = FrameSize + SPUFrameInfo::minStackSize();
FrameSize = FrameSize + SPUFrameLowering::minStackSize();
if (isInt<10>(FrameSize + LinkSlotOffset)) {
// Reload $lr, adjust $sp by required amount
// Note: We do this to slightly improve dual issue -- not by much, but it
@ -250,14 +250,15 @@ void SPUFrameInfo::emitEpilogue(MachineFunction &MF,
}
}
void SPUFrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
void SPUFrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves)
const {
// Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(SPU::R1, 0);
Moves.push_back(MachineMove(0, Dst, Src));
}
void SPUFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
void SPUFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const{
// Mark LR and SP unused, since the prolog spills them to stack and
// we don't want anyone else to spill them for us.

8
lib/Target/CellSPU/SPUFrameInfo.h → lib/Target/CellSPU/SPUFrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==//
//=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#define SPU_FRAMEINFO_H
#include "SPURegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class SPUSubtarget;
class SPUFrameInfo: public TargetFrameInfo {
class SPUFrameLowering: public TargetFrameLowering {
const SPUSubtarget &Subtarget;
std::pair<unsigned, int> LR[1];
public:
SPUFrameInfo(const SPUSubtarget &sti);
SPUFrameLowering(const SPUSubtarget &sti);
//! Determine the frame's layour
void determineFrameLayout(MachineFunction &MF) const;

12
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -15,7 +15,7 @@
#include "SPU.h"
#include "SPUTargetMachine.h"
#include "SPUHazardRecognizers.h"
#include "SPUFrameInfo.h"
#include "SPUFrameLowering.h"
#include "SPURegisterNames.h"
#include "SPUTargetMachine.h"
#include "llvm/CodeGen/MachineConstantPool.h"
@ -390,8 +390,8 @@ bool
SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
SDValue &Index) {
return DFormAddressPredicate(Op, N, Base, Index,
SPUFrameInfo::minFrameOffset(),
SPUFrameInfo::maxFrameOffset());
SPUFrameLowering::minFrameOffset(),
SPUFrameLowering::maxFrameOffset());
}
bool
@ -407,7 +407,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
int FI = int(FIN->getIndex());
DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
<< FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
Base = CurDAG->getTargetConstant(0, PtrTy);
Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
return true;
@ -433,7 +433,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
<< " frame index = " << FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
Base = CurDAG->getTargetConstant(offset, PtrTy);
Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
return true;
@ -454,7 +454,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
<< " frame index = " << FI << "\n");
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
Base = CurDAG->getTargetConstant(offset, PtrTy);
Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
return true;

13
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1,4 +1,3 @@
//
//===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
// The LLVM Compiler Infrastructure
//
@ -14,7 +13,7 @@
#include "SPURegisterNames.h"
#include "SPUISelLowering.h"
#include "SPUTargetMachine.h"
#include "SPUFrameInfo.h"
#include "SPUFrameLowering.h"
#include "SPUMachineFunction.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
@ -1123,9 +1122,9 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
MachineRegisterInfo &RegInfo = MF.getRegInfo();
SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>();
unsigned ArgOffset = SPUFrameInfo::minStackSize();
unsigned ArgOffset = SPUFrameLowering::minStackSize();
unsigned ArgRegIdx = 0;
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
unsigned StackSlotSize = SPUFrameLowering::stackSlotSize();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@ -1274,7 +1273,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
unsigned NumOps = Outs.size();
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
unsigned StackSlotSize = SPUFrameLowering::stackSlotSize();
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
@ -1295,7 +1294,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// Figure out which arguments are going to go in registers, and which in
// memory.
unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
unsigned ArgOffset = SPUFrameLowering::minStackSize(); // Just below [LR]
unsigned ArgRegIdx = 0;
// Keep track of registers passing arguments
@ -1342,7 +1341,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// Accumulate how many bytes are to be pushed on the stack, including the
// linkage area, and parameter passing area. According to the SPU ABI,
// we minimally need space for [LR] and [SP].
unsigned NumStackBytes = ArgOffset - SPUFrameInfo::minStackSize();
unsigned NumStackBytes = ArgOffset - SPUFrameLowering::minStackSize();
// Insert a call sequence start
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes,

4
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -140,7 +140,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI) const
{
unsigned opc;
bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
if (RC == SPU::GPRCRegisterClass) {
opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
} else if (RC == SPU::R64CRegisterClass) {
@ -175,7 +175,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI) const
{
unsigned opc;
bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
if (RC == SPU::GPRCRegisterClass) {
opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
} else if (RC == SPU::R64CRegisterClass) {

6
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -18,7 +18,7 @@
#include "SPUInstrBuilder.h"
#include "SPUSubtarget.h"
#include "SPUMachineFunction.h"
#include "SPUFrameInfo.h"
#include "SPUFrameLowering.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
#include "llvm/CodeGen/ValueTypes.h"
@ -30,7 +30,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@ -283,7 +283,7 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
MachineOperand &MO = MI.getOperand(OpNo);
// Offset is biased by $lr's slot at the bottom.
Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize();
assert((Offset & 0xf) == 0
&& "16-byte alignment violated in eliminateFrameIndex");

4
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -29,7 +29,7 @@ extern "C" void LLVMInitializeCellSPUTarget() {
}
const std::pair<unsigned, int> *
SPUFrameInfo::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
NumEntries = 1;
return &LR[0];
}
@ -40,7 +40,7 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
Subtarget(TT, FS),
DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this),
FrameInfo(Subtarget),
FrameLowering(Subtarget),
TLInfo(*this),
TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {

10
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -18,14 +18,14 @@
#include "SPUInstrInfo.h"
#include "SPUISelLowering.h"
#include "SPUSelectionDAGInfo.h"
#include "SPUFrameInfo.h"
#include "SPUFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
namespace llvm {
class PassManager;
class GlobalValue;
class TargetFrameInfo;
class TargetFrameLowering;
/// SPUTargetMachine
///
@ -33,7 +33,7 @@ class SPUTargetMachine : public LLVMTargetMachine {
SPUSubtarget Subtarget;
const TargetData DataLayout;
SPUInstrInfo InstrInfo;
SPUFrameInfo FrameInfo;
SPUFrameLowering FrameLowering;
SPUTargetLowering TLInfo;
SPUSelectionDAGInfo TSInfo;
InstrItineraryData InstrItins;
@ -48,8 +48,8 @@ public:
virtual const SPUInstrInfo *getInstrInfo() const {
return &InstrInfo;
}
virtual const SPUFrameInfo *getFrameInfo() const {
return &FrameInfo;
virtual const SPUFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
/*!
\note Cell SPU does not support JIT today. It could support JIT at some

2
lib/Target/MBlaze/MBlazeAsmPrinter.cpp
View File

@ -125,7 +125,7 @@ static void printHex32(unsigned int Value, raw_ostream &O) {
// Create a bitmask with all callee saved registers for CPU or Floating Point
// registers. For CPU registers consider RA, GP and FP for saving if necessary.
void MBlazeAsmPrinter::printSavedRegsBitmask() {
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
// CPU Saved Registers Bitmasks

21
lib/Target/MBlaze/MBlazeFrameInfo.cpp → lib/Target/MBlaze/MBlazeFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- MBlazeFrameInfo.cpp - MBlaze Frame Information ------*- C++ -*-====//
//=======- MBlazeFrameLowering.cpp - MBlaze Frame Information ------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,13 +7,13 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the MBlaze implementation of TargetFrameInfo class.
// This file contains the MBlaze implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "mblaze-frame-info"
#define DEBUG_TYPE "mblaze-frame-lowering"
#include "MBlazeFrameInfo.h"
#include "MBlazeFrameLowering.h"
#include "MBlazeInstrInfo.h"
#include "MBlazeMachineFunction.h"
#include "InstPrinter/MBlazeInstPrinter.h"
@ -314,7 +314,7 @@ static void determineFrameLayout(MachineFunction &MF) {
// Get the alignments provided by the target, and the maximum alignment
// (if any) of the fixed frame objects.
// unsigned MaxAlign = MFI->getMaxAlignment();
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
unsigned AlignMask = TargetAlign - 1;
// Make sure the frame is aligned.
@ -334,12 +334,12 @@ int MBlazeFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI)
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool MBlazeFrameInfo::hasFP(const MachineFunction &MF) const {
bool MBlazeFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
}
void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const {
void MBlazeFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
const MBlazeInstrInfo &TII =
@ -384,7 +384,7 @@ void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF,
void MBlazeFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -427,8 +427,9 @@ void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF,
}
}
void MBlazeFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS)
const {
void MBlazeFrameLowering::
processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv();

10
lib/Target/MBlaze/MBlazeFrameInfo.h → lib/Target/MBlaze/MBlazeFrameLowering.h
View File

@ -1,4 +1,4 @@
//=-- MBlazeFrameInfo.h - Define TargetFrameInfo for MicroBlaze --*- C++ -*--=//
//=- MBlazeFrameLowering.h - Define frame lowering for MicroBlaze -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "MBlaze.h"
#include "MBlazeSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class MBlazeSubtarget;
class MBlazeFrameInfo : public TargetFrameInfo {
class MBlazeFrameLowering : public TargetFrameLowering {
protected:
const MBlazeSubtarget &STI;
public:
explicit MBlazeFrameInfo(const MBlazeSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsUp, 4, 0), STI(sti) {
explicit MBlazeFrameLowering(const MBlazeSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
}
/// targetHandlesStackFrameRounding - Returns true if the target is

2
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -697,7 +697,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;

10
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -1,5 +1,5 @@
//===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===//
//DJ
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
@ -26,7 +26,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -223,7 +223,7 @@ getReservedRegs(const MachineFunction &MF) const {
void MBlazeRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!TFI->hasReservedCallFrame(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
@ -235,7 +235,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = TFI->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
MachineInstr *New;
@ -317,7 +317,7 @@ unsigned MBlazeRegisterInfo::getRARegister() const {
}
unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? MBlaze::R19 : MBlaze::R1;
}

2
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -85,7 +85,7 @@ MBlazeTargetMachine(const Target &T, const std::string &TT,
Subtarget(TT, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this),
FrameInfo(Subtarget),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this) {
if (getRelocationModel() == Reloc::Default) {
setRelocationModel(Reloc::Static);

20
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -19,24 +19,24 @@
#include "MBlazeISelLowering.h"
#include "MBlazeSelectionDAGInfo.h"
#include "MBlazeIntrinsicInfo.h"
#include "MBlazeFrameInfo.h"
#include "MBlazeFrameLowering.h"
#include "MBlazeELFWriterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class formatted_raw_ostream;
class MBlazeTargetMachine : public LLVMTargetMachine {
MBlazeSubtarget Subtarget;
const TargetData DataLayout; // Calculates type size & alignment
MBlazeInstrInfo InstrInfo;
MBlazeFrameInfo FrameInfo;
MBlazeTargetLowering TLInfo;
MBlazeSubtarget Subtarget;
const TargetData DataLayout; // Calculates type size & alignment
MBlazeInstrInfo InstrInfo;
MBlazeFrameLowering FrameLowering;
MBlazeTargetLowering TLInfo;
MBlazeSelectionDAGInfo TSInfo;
MBlazeIntrinsicInfo IntrinsicInfo;
MBlazeIntrinsicInfo IntrinsicInfo;
MBlazeELFWriterInfo ELFWriterInfo;
public:
MBlazeTargetMachine(const Target &T, const std::string &TT,
@ -45,8 +45,8 @@ namespace llvm {
virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const
{ return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const
{ return &FrameLowering; }
virtual const MBlazeSubtarget *getSubtargetImpl() const
{ return &Subtarget; }

22
lib/Target/MSP430/MSP430FrameInfo.cpp → lib/Target/MSP430/MSP430FrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- MSP430FrameInfo.cpp - MSP430 Frame Information ------*- C++ -*-====//
//======-- MSP430FrameLowering.cpp - MSP430 Frame Information -------=========//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the MSP430 implementation of TargetFrameInfo class.
// This file contains the MSP430 implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "MSP430FrameInfo.h"
#include "MSP430FrameLowering.h"
#include "MSP430InstrInfo.h"
#include "MSP430MachineFunctionInfo.h"
#include "llvm/Function.h"
@ -26,7 +26,7 @@
using namespace llvm;
bool MSP430FrameInfo::hasFP(const MachineFunction &MF) const {
bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return (DisableFramePointerElim(MF) ||
@ -34,11 +34,11 @@ bool MSP430FrameInfo::hasFP(const MachineFunction &MF) const {
MFI->isFrameAddressTaken());
}
bool MSP430FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo()->hasVarSizedObjects();
}
void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const {
void MSP430FrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineFrameInfo *MFI = MF.getFrameInfo();
MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
@ -103,8 +103,8 @@ void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void MSP430FrameInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
const MSP430InstrInfo &TII =
@ -177,7 +177,7 @@ void MSP430FrameInfo::emitEpilogue(MachineFunction &MF,
// FIXME: Can we eleminate these in favour of generic code?
bool
MSP430FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -203,8 +203,8 @@ MSP430FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
}
bool
MSP430FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
if (CSI.empty())

10
lib/Target/MSP430/MSP430FrameInfo.h → lib/Target/MSP430/MSP430FrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- MSP430FrameInfo.h - Define TargetFrameInfo for MSP430 --*- C++ -*--===//
//==- MSP430FrameLowering.h - Define frame lowering for MSP430 --*- C++ -*--==//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "MSP430.h"
#include "MSP430Subtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class MSP430Subtarget;
class MSP430FrameInfo : public TargetFrameInfo {
class MSP430FrameLowering : public TargetFrameLowering {
protected:
const MSP430Subtarget &STI;
public:
explicit MSP430FrameInfo(const MSP430Subtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) {
explicit MSP430FrameLowering(const MSP430Subtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

14
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -33,12 +33,12 @@ MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
TM(tm), TII(tii) {
StackAlign = TM.getFrameInfo()->getStackAlignment();
StackAlign = TM.getFrameLowering()->getStackAlignment();
}
const unsigned*
MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const TargetFrameInfo *TFI = MF->getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
const Function* F = MF->getFunction();
static const unsigned CalleeSavedRegs[] = {
MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
@ -74,7 +74,7 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
// Mark 4 special registers as reserved.
Reserved.set(MSP430::PCW);
@ -97,7 +97,7 @@ MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
void MSP430RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!TFI->hasReservedCallFrame(MF)) {
// If the stack pointer can be changed after prologue, turn the
@ -163,7 +163,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
DebugLoc dl = MI.getDebugLoc();
while (!MI.getOperand(i).isFI()) {
++i;
@ -216,7 +216,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
void
MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
// Create a frame entry for the FPW register that must be saved.
if (TFI->hasFP(MF)) {
@ -232,7 +232,7 @@ unsigned MSP430RegisterInfo::getRARegister() const {
}
unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
}

4
lib/Target/MSP430/MSP430RegisterInfo.td
View File

@ -79,7 +79,7 @@ def GR8 : RegisterClass<"MSP430", [i8], 8,
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
if (TFI->hasFP(MF))
@ -106,7 +106,7 @@ def GR16 : RegisterClass<"MSP430", [i16], 16,
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
if (TFI->hasFP(MF))

2
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
// FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameInfo(Subtarget) { }
FrameLowering(Subtarget) { }
bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM,

10
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -17,12 +17,12 @@
#include "MSP430InstrInfo.h"
#include "MSP430ISelLowering.h"
#include "MSP430FrameInfo.h"
#include "MSP430FrameLowering.h"
#include "MSP430SelectionDAGInfo.h"
#include "MSP430RegisterInfo.h"
#include "MSP430Subtarget.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -35,13 +35,15 @@ class MSP430TargetMachine : public LLVMTargetMachine {
MSP430InstrInfo InstrInfo;
MSP430TargetLowering TLInfo;
MSP430SelectionDAGInfo TSInfo;
MSP430FrameInfo FrameInfo;
MSP430FrameLowering FrameLowering;
public:
MSP430TargetMachine(const Target &T, const std::string &TT,
const std::string &FS);
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const MSP430InstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetData *getTargetData() const { return &DataLayout;}
virtual const MSP430Subtarget *getSubtargetImpl() const { return &Subtarget; }

4
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -125,7 +125,7 @@ namespace {
// Create a bitmask with all callee saved registers for CPU or Floating Point
// registers. For CPU registers consider RA, GP and FP for saving if necessary.
void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
const MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
@ -146,6 +146,8 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
}
// Return Address and Frame registers must also be set in CPUBitmask.
// FIXME: Do we really need hasFP() call here? When no FP is present SP is
// just returned -- will it be ok?
if (TFI->hasFP(*MF))
CPUBitmask |= (1 << MipsRegisterInfo::
getRegisterNumbering(RI->getFrameRegister(*MF)));

16
lib/Target/Mips/MipsFrameInfo.cpp → lib/Target/Mips/MipsFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- MipsFrameInfo.cpp - Mips Frame Information ----------*- C++ -*-====//
//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Mips implementation of TargetFrameInfo class.
// This file contains the Mips implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "MipsFrameInfo.h"
#include "MipsFrameLowering.h"
#include "MipsInstrInfo.h"
#include "MipsMachineFunction.h"
#include "llvm/Function.h"
@ -82,16 +82,16 @@ using namespace llvm;
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool MipsFrameInfo::hasFP(const MachineFunction &MF) const {
bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
}
void MipsFrameInfo::adjustMipsStackFrame(MachineFunction &MF) const {
void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned StackAlign = getStackAlignment();
unsigned RegSize = STI.isGP32bit() ? 4 : 8;
bool HasGP = MipsFI->needGPSaveRestore();
@ -203,7 +203,7 @@ void MipsFrameInfo::adjustMipsStackFrame(MachineFunction &MF) const {
MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
}
void MipsFrameInfo::emitPrologue(MachineFunction &MF) const {
void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
@ -264,7 +264,7 @@ void MipsFrameInfo::emitPrologue(MachineFunction &MF) const {
.addImm(MipsFI->getGPStackOffset());
}
void MipsFrameInfo::emitEpilogue(MachineFunction &MF,
void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineFrameInfo *MFI = MF.getFrameInfo();

10
lib/Target/Mips/MipsFrameInfo.h → lib/Target/Mips/MipsFrameLowering.h
View File

@ -1,4 +1,4 @@
//====--- MipsFrameInfo.h - Define TargetFrameInfo for Mips --*- C++ -*---====//
//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===//
//
// The LLVM Compiler Infrastructure
//
@ -16,19 +16,19 @@
#include "Mips.h"
#include "MipsSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class MipsSubtarget;
class MipsFrameInfo : public TargetFrameInfo {
class MipsFrameLowering : public TargetFrameLowering {
protected:
const MipsSubtarget &STI;
public:
explicit MipsFrameInfo(const MipsSubtarget &sti)
explicit MipsFrameLowering(const MipsSubtarget &sti)
// FIXME: Is this correct at all?
: TargetFrameInfo(StackGrowsUp, 8, 0), STI(sti) {
: TargetFrameLowering(StackGrowsUp, 8, 0), STI(sti) {
}
void adjustMipsStackFrame(MachineFunction &MF) const;

4
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -25,7 +25,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -199,7 +199,7 @@ getRARegister() const {
unsigned MipsRegisterInfo::
getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
}

2
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -41,7 +41,7 @@ MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS,
DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") :
std::string("E-p:32:32:32-i8:8:32-i16:16:32-n32")),
InstrInfo(*this),
FrameInfo(Subtarget),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this) {
// Abicall enables PIC by default
if (getRelocationModel() == Reloc::Default) {

10
lib/Target/Mips/MipsTargetMachine.h
View File

@ -17,11 +17,11 @@
#include "MipsSubtarget.h"
#include "MipsInstrInfo.h"
#include "MipsISelLowering.h"
#include "MipsFrameInfo.h"
#include "MipsFrameLowering.h"
#include "MipsSelectionDAGInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class formatted_raw_ostream;
@ -30,7 +30,7 @@ namespace llvm {
MipsSubtarget Subtarget;
const TargetData DataLayout; // Calculates type size & alignment
MipsInstrInfo InstrInfo;
MipsFrameInfo FrameInfo;
MipsFrameLowering FrameLowering;
MipsTargetLowering TLInfo;
MipsSelectionDAGInfo TSInfo;
public:
@ -39,8 +39,8 @@ namespace llvm {
virtual const MipsInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const
{ return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const
{ return &FrameLowering; }
virtual const MipsSubtarget *getSubtargetImpl() const
{ return &Subtarget; }
virtual const TargetData *getTargetData() const

12
lib/Target/PTX/PTXFrameInfo.cpp → lib/Target/PTX/PTXFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- PTXFrameInfo.cpp - PTX Frame Information -----------*- C++ -*-=====//
//=======- PTXFrameLowering.cpp - PTX Frame Information -------*- C++ -*-=====//
//
// The LLVM Compiler Infrastructure
//
@ -7,18 +7,18 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the PTX implementation of TargetFrameInfo class.
// This file contains the PTX implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "PTXFrameInfo.h"
#include "PTXFrameLowering.h"
#include "llvm/CodeGen/MachineFunction.h"
using namespace llvm;
void PTXFrameInfo::emitPrologue(MachineFunction &MF) const {
void PTXFrameLowering::emitPrologue(MachineFunction &MF) const {
}
void PTXFrameInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
void PTXFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
}

10
lib/Target/PTX/PTXFrameInfo.h → lib/Target/PTX/PTXFrameLowering.h
View File

@ -1,4 +1,4 @@
//====---- PTXFrameInfo.h - Define TargetFrameInfo for PTX --*- C++ -*----====//
//===--- PTXFrameLowering.h - Define frame lowering for PTX --*- C++ -*----===//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "PTX.h"
#include "PTXSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class PTXSubtarget;
class PTXFrameInfo : public TargetFrameInfo {
class PTXFrameLowering : public TargetFrameLowering {
protected:
const PTXSubtarget &STI;
public:
explicit PTXFrameInfo(const PTXSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) {
explicit PTXFrameLowering(const PTXSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

4
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -34,13 +34,13 @@ extern "C" void LLVMInitializePTXTarget() {
TargetRegistry::RegisterAsmStreamer(ThePTXTarget, createPTXAsmStreamer);
}
// DataLayout and FrameInfo are filled with dummy data
// DataLayout and FrameLowering are filled with dummy data
PTXTargetMachine::PTXTargetMachine(const Target &T,
const std::string &TT,
const std::string &FS)
: LLVMTargetMachine(T, TT),
DataLayout("e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64"),
FrameInfo(Subtarget),
FrameLowering(Subtarget),
InstrInfo(*this),
TLInfo(*this),
Subtarget(TT, FS) {

10
lib/Target/PTX/PTXTargetMachine.h
View File

@ -16,17 +16,17 @@
#include "PTXISelLowering.h"
#include "PTXInstrInfo.h"
#include "PTXFrameInfo.h"
#include "PTXFrameLowering.h"
#include "PTXSubtarget.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class PTXTargetMachine : public LLVMTargetMachine {
private:
const TargetData DataLayout;
PTXFrameInfo FrameInfo;
PTXFrameLowering FrameLowering;
PTXInstrInfo InstrInfo;
PTXTargetLowering TLInfo;
PTXSubtarget Subtarget;
@ -37,7 +37,9 @@ class PTXTargetMachine : public LLVMTargetMachine {
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const PTXInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetRegisterInfo *getRegisterInfo() const {

40
lib/Target/PowerPC/PPCFrameInfo.cpp → lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- PPCFrameInfo.cpp - PPC Frame Information ------------*- C++ -*-====//
//=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the PPC implementation of TargetFrameInfo class.
// This file contains the PPC implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "PPCFrameInfo.h"
#include "PPCFrameLowering.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "llvm/Function.h"
@ -170,7 +170,7 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.
void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const {
void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
// Get the number of bytes to allocate from the FrameInfo
@ -179,7 +179,7 @@ void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const {
// Get the alignments provided by the target, and the maximum alignment
// (if any) of the fixed frame objects.
unsigned MaxAlign = MFI->getMaxAlignment();
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = getStackAlignment();
unsigned AlignMask = TargetAlign - 1; //
// If we are a leaf function, and use up to 224 bytes of stack space,
@ -225,7 +225,7 @@ void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const {
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register.
bool PPCFrameInfo::hasFP(const MachineFunction &MF) const {
bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
// FIXME: This is pretty much broken by design: hasFP() might be called really
// early, before the stack layout was calculated and thus hasFP() might return
@ -236,7 +236,7 @@ bool PPCFrameInfo::hasFP(const MachineFunction &MF) const {
// needsFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool PPCFrameInfo::needsFP(const MachineFunction &MF) const {
bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
// Naked functions have no stack frame pushed, so we don't have a frame
@ -249,7 +249,7 @@ bool PPCFrameInfo::needsFP(const MachineFunction &MF) const {
}
void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -295,7 +295,7 @@ void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF);
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
@ -305,7 +305,7 @@ void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
}
}
@ -345,7 +345,7 @@ void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
if (!FrameSize) return;
// Get stack alignments.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = getStackAlignment();
unsigned MaxAlign = MFI->getMaxAlignment();
// Adjust stack pointer: r1 += NegFrameSize.
@ -495,7 +495,7 @@ void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
const PPCInstrInfo &TII =
@ -515,7 +515,7 @@ void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
// Get alignment info so we know how to restore r1
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = getStackAlignment();
unsigned MaxAlign = MFI->getMaxAlignment();
// Get the number of bytes allocated from the FrameInfo.
@ -531,7 +531,7 @@ void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF);
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
@ -541,7 +541,7 @@ void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
}
}
@ -704,7 +704,7 @@ void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
}
}
void PPCFrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
void PPCFrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves) const {
// Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(PPC::R1, 0);
@ -731,7 +731,7 @@ static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
}
void
PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
@ -752,7 +752,7 @@ PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Find out what the fix offset of the frame pointer save area.
int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
// Allocate the frame index for frame pointer save area.
FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
// Save the result.
FI->setFramePointerSaveIndex(FPSI);
}
@ -760,7 +760,7 @@ PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Reserve stack space to move the linkage area to in case of a tail call.
int TCSPDelta = 0;
if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
}
// Reserve a slot closest to SP or frame pointer if we have a dynalloc or
@ -781,7 +781,7 @@ PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
}
}
void PPCFrameInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF)
const {
// Early exit if not using the SVR4 ABI.
if (!Subtarget.isSVR4ABI())

11
lib/Target/PowerPC/PPCFrameInfo.h → lib/Target/PowerPC/PPCFrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===//
//==-- PPCFrameLowering.h - Define frame lowering for PowerPC ----*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -15,19 +15,20 @@
#include "PPC.h"
#include "PPCSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
namespace llvm {
class PPCSubtarget;
class PPCFrameInfo: public TargetFrameInfo {
class PPCFrameLowering: public TargetFrameLowering {
const PPCSubtarget &Subtarget;
public:
PPCFrameInfo(const PPCSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), Subtarget(sti) {
PPCFrameLowering(const PPCSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0),
Subtarget(sti) {
}
void determineFrameLayout(MachineFunction &MF) const;

32
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1565,7 +1565,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
*DAG.getContext());
// Reserve space for the linkage area on the stack.
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
@ -1641,9 +1641,9 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
MinReservedArea =
std::max(MinReservedArea,
PPCFrameInfo::getMinCallFrameSize(false, false));
PPCFrameLowering::getMinCallFrameSize(false, false));
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
getStackAlignment();
unsigned AlignMask = TargetAlign-1;
MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
@ -1749,7 +1749,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
unsigned PtrByteSize = isPPC64 ? 8 : 4;
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
// Area that is at least reserved in caller of this function.
unsigned MinReservedArea = ArgOffset;
@ -2041,8 +2041,8 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
}
MinReservedArea =
std::max(MinReservedArea,
PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
getStackAlignment();
unsigned AlignMask = TargetAlign-1;
MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
@ -2100,7 +2100,7 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
// Count how many bytes are to be pushed on the stack, including the linkage
// area, and parameter passing area. We start with 24/48 bytes, which is
// prereserved space for [SP][CR][LR][3 x unused].
unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
unsigned NumOps = Outs.size();
unsigned PtrByteSize = isPPC64 ? 8 : 4;
@ -2141,11 +2141,11 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
// conservatively assume that it is needed. As such, make sure we have at
// least enough stack space for the caller to store the 8 GPRs.
NumBytes = std::max(NumBytes,
PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
// Tail call needs the stack to be aligned.
if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
getStackAlignment();
unsigned AlignMask = TargetAlign-1;
NumBytes = (NumBytes + AlignMask) & ~AlignMask;
@ -2269,7 +2269,7 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
if (SPDiff) {
// Calculate the new stack slot for the return address.
int SlotSize = isPPC64 ? 8 : 4;
int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
isDarwinABI);
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
NewRetAddrLoc, true);
@ -2283,7 +2283,7 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
// slot as the FP is never overwritten.
if (isDarwinABI) {
int NewFPLoc =
SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
true);
SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
@ -2760,7 +2760,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
ArgLocs, *DAG.getContext());
// Reserve space for the linkage area on the stack.
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
if (isVarArg) {
// Handle fixed and variable vector arguments differently.
@ -2997,7 +2997,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
// memory. Also, if this is a vararg function, floating point operations
// must be stored to our stack, and loaded into integer regs as well, if
// any integer regs are available for argument passing.
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
static const unsigned GPR_32[] = { // 32-bit registers.
@ -3379,7 +3379,7 @@ PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
// If the frame pointer save index hasn't been defined yet.
if (!RASI) {
// Find out what the fix offset of the frame pointer save area.
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
// Allocate the frame index for frame pointer save area.
RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
// Save the result.
@ -3403,7 +3403,7 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
// If the frame pointer save index hasn't been defined yet.
if (!FPSI) {
// Find out what the fix offset of the frame pointer save area.
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
isDarwinABI);
// Allocate the frame index for frame pointer save area.
@ -5567,7 +5567,7 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset =
DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI),
DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
isPPC64? MVT::i64 : MVT::i32);
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, getPointerTy(),

14
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -17,7 +17,7 @@
#include "PPCInstrBuilder.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCRegisterInfo.h"
#include "PPCFrameInfo.h"
#include "PPCFrameLowering.h"
#include "PPCSubtarget.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
@ -31,7 +31,7 @@
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@ -258,8 +258,8 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const PPCFrameInfo *PPCFI =
static_cast<const PPCFrameInfo*>(MF.getTarget().getFrameInfo());
const PPCFrameLowering *PPCFI =
static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
Reserved.set(PPC::R0);
Reserved.set(PPC::R1);
@ -395,7 +395,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
unsigned FrameSize = MFI->getStackSize();
// Get stack alignments.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
unsigned MaxAlign = MFI->getMaxAlignment();
if (MaxAlign > TargetAlign)
report_fatal_error("Dynamic alloca with large aligns not supported");
@ -541,7 +541,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineFunction &MF = *MBB.getParent();
// Get the frame info.
MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
DebugLoc dl = MI.getDebugLoc();
// Find out which operand is the frame index.
@ -670,7 +670,7 @@ unsigned PPCRegisterInfo::getRARegister() const {
}
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (!Subtarget.isPPC64())
return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;

8
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -301,8 +301,8 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
// When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
// pointer.
const PPCSubtarget &Subtarget = MF.getTarget().getSubtarget<PPCSubtarget>();
const PPCFrameInfo *PPCFI =
static_cast<const PPCFrameInfo*>(MF.getTarget().getFrameInfo());
const PPCFrameLowering *PPCFI =
static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
return end()-5; // don't allocate R13, R31, R0, R1, LR
@ -332,8 +332,8 @@ def G8RC : RegisterClass<"PPC", [i64], 64,
}
G8RCClass::iterator
G8RCClass::allocation_order_end(const MachineFunction &MF) const {
const PPCFrameInfo *PPCFI =
static_cast<const PPCFrameInfo*>(MF.getTarget().getFrameInfo());
const PPCFrameLowering *PPCFI =
static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
if (PPCFI->needsFP(MF))
return end()-5;
else

2
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -72,7 +72,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
: LLVMTargetMachine(T, TT),
Subtarget(TT, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameInfo(Subtarget), JITInfo(*this, is64Bit),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {

14
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -14,7 +14,7 @@
#ifndef PPC_TARGETMACHINE_H
#define PPC_TARGETMACHINE_H
#include "PPCFrameInfo.h"
#include "PPCFrameLowering.h"
#include "PPCSubtarget.h"
#include "PPCJITInfo.h"
#include "PPCInstrInfo.h"
@ -33,7 +33,7 @@ class PPCTargetMachine : public LLVMTargetMachine {
PPCSubtarget Subtarget;
const TargetData DataLayout; // Calculates type size & alignment
PPCInstrInfo InstrInfo;
PPCFrameInfo FrameInfo;
PPCFrameLowering FrameLowering;
PPCJITInfo JITInfo;
PPCTargetLowering TLInfo;
PPCSelectionDAGInfo TSInfo;
@ -43,16 +43,18 @@ public:
PPCTargetMachine(const Target &T, const std::string &TT,
const std::string &FS, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
virtual const PPCTargetLowering *getTargetLowering() const {
return &TLInfo;
}
virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const {
return &TSInfo;
}
virtual const PPCRegisterInfo *getRegisterInfo() const {
virtual const PPCRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}

10
lib/Target/Sparc/SparcFrameInfo.cpp → lib/Target/Sparc/SparcFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- SparcFrameInfo.cpp - Sparc Frame Information --------*- C++ -*-====//
//====- SparcFrameLowering.cpp - Sparc Frame Information -------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Sparc implementation of TargetFrameInfo class.
// This file contains the Sparc implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "SparcFrameInfo.h"
#include "SparcFrameLowering.h"
#include "SparcInstrInfo.h"
#include "SparcMachineFunctionInfo.h"
#include "llvm/Function.h"
@ -26,7 +26,7 @@
using namespace llvm;
void SparcFrameInfo::emitPrologue(MachineFunction &MF) const {
void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
const SparcInstrInfo &TII =
@ -67,7 +67,7 @@ void SparcFrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void SparcFrameInfo::emitEpilogue(MachineFunction &MF,
void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
const SparcInstrInfo &TII =

10
lib/Target/Sparc/SparcFrameInfo.h → lib/Target/Sparc/SparcFrameLowering.h
View File

@ -1,4 +1,4 @@
//===--- SparcFrameInfo.h - Define TargetFrameInfo for Sparc --*- C++ -*---===//
//===- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
@ -16,16 +16,16 @@
#include "Sparc.h"
#include "SparcSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class SparcSubtarget;
class SparcFrameInfo : public TargetFrameInfo {
class SparcFrameLowering : public TargetFrameLowering {
const SparcSubtarget &STI;
public:
explicit SparcFrameInfo(const SparcSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), STI(sti) {
explicit SparcFrameLowering(const SparcSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into

2
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -35,7 +35,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
Subtarget(TT, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
FrameInfo(Subtarget) {
FrameLowering(Subtarget) {
}
bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,

10
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -16,12 +16,12 @@
#include "SparcInstrInfo.h"
#include "SparcISelLowering.h"
#include "SparcFrameInfo.h"
#include "SparcFrameLowering.h"
#include "SparcSelectionDAGInfo.h"
#include "SparcSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
@ -31,13 +31,15 @@ class SparcTargetMachine : public LLVMTargetMachine {
SparcTargetLowering TLInfo;
SparcSelectionDAGInfo TSInfo;
SparcInstrInfo InstrInfo;
SparcFrameInfo FrameInfo;
SparcFrameLowering FrameLowering;
public:
SparcTargetMachine(const Target &T, const std::string &TT,
const std::string &FS, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual const SparcRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();

30
lib/Target/SystemZ/SystemZFrameInfo.cpp → lib/Target/SystemZ/SystemZFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=====- SystemZFrameInfo.cpp - SystemZ Frame Information ------*- C++ -*-====//
//=====- SystemZFrameLowering.cpp - SystemZ Frame Information ------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the SystemZ implementation of TargetFrameInfo class.
// This file contains the SystemZ implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "SystemZFrameInfo.h"
#include "SystemZFrameLowering.h"
#include "SystemZInstrBuilder.h"
#include "SystemZInstrInfo.h"
#include "SystemZMachineFunctionInfo.h"
@ -27,8 +27,8 @@
using namespace llvm;
SystemZFrameInfo::SystemZFrameInfo(const SystemZSubtarget &sti)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160), STI(sti) {
SystemZFrameLowering::SystemZFrameLowering(const SystemZSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, -160), STI(sti) {
// Fill the spill offsets map
static const unsigned SpillOffsTab[][2] = {
{ SystemZ::R2D, 0x10 },
@ -56,7 +56,7 @@ SystemZFrameInfo::SystemZFrameInfo(const SystemZSubtarget &sti)
/// needsFP - Return true if the specified function should have a dedicated
/// frame pointer register. This is true if the function has variable sized
/// allocas or if frame pointer elimination is disabled.
bool SystemZFrameInfo::hasFP(const MachineFunction &MF) const {
bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
}
@ -91,9 +91,8 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
}
}
void SystemZFrameInfo::emitPrologue(MachineFunction &MF) const {
void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
const SystemZInstrInfo &TII =
*static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo());
@ -108,7 +107,7 @@ void SystemZFrameInfo::emitPrologue(MachineFunction &MF) const {
uint64_t StackSize = MFI->getStackSize();
StackSize -= SystemZMFI->getCalleeSavedFrameSize();
uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea();
uint64_t NumBytes = StackSize - getOffsetOfLocalArea();
// Skip the callee-saved push instructions.
while (MBBI != MBB.end() &&
@ -139,10 +138,9 @@ void SystemZFrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void SystemZFrameInfo::emitEpilogue(MachineFunction &MF,
void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
const SystemZInstrInfo &TII =
*static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo());
@ -161,7 +159,7 @@ void SystemZFrameInfo::emitEpilogue(MachineFunction &MF,
// 'undo' the stack movement.
uint64_t StackSize =
MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize();
uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea();
uint64_t NumBytes = StackSize - getOffsetOfLocalArea();
// Skip the final terminator instruction.
while (MBBI != MBB.begin()) {
@ -202,7 +200,7 @@ void SystemZFrameInfo::emitEpilogue(MachineFunction &MF,
}
}
int SystemZFrameInfo::getFrameIndexOffset(const MachineFunction &MF,
int SystemZFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
int FI) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const SystemZMachineFunctionInfo *SystemZMFI =
@ -224,7 +222,7 @@ int SystemZFrameInfo::getFrameIndexOffset(const MachineFunction &MF,
}
bool
SystemZFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
SystemZFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -299,7 +297,7 @@ SystemZFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
}
bool
SystemZFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
SystemZFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -353,7 +351,7 @@ SystemZFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
}
void
SystemZFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
SystemZFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
// Determine whether R15/R14 will ever be clobbered inside the function. And
// if yes - mark it as 'callee' saved.

8
lib/Target/SystemZ/SystemZFrameInfo.h → lib/Target/SystemZ/SystemZFrameLowering.h
View File

@ -1,4 +1,4 @@
//==- SystemZFrameInfo.h - Define TargetFrameInfo for z/System --*- C++ -*--==//
//=- SystemZFrameLowering.h - Define frame lowering for z/System -*- C++ -*--=//
//
// The LLVM Compiler Infrastructure
//
@ -16,19 +16,19 @@
#include "SystemZ.h"
#include "SystemZSubtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/ADT/IndexedMap.h"
namespace llvm {
class SystemZSubtarget;
class SystemZFrameInfo : public TargetFrameInfo {
class SystemZFrameLowering : public TargetFrameLowering {
IndexedMap<unsigned> RegSpillOffsets;
protected:
const SystemZSubtarget &STI;
public:
explicit SystemZFrameInfo(const SystemZSubtarget &sti);
explicit SystemZFrameLowering(const SystemZSubtarget &sti);
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.

2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -378,7 +378,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
// Offset to first argument stack slot.
const unsigned FirstArgOffset = 160;

6
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -20,7 +20,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@ -49,7 +49,7 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (TFI->hasFP(MF))
Reserved.set(SystemZ::R11D);
@ -72,7 +72,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned i = 0;
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
while (!MI.getOperand(i).isFI()) {
++i;

24
lib/Target/SystemZ/SystemZRegisterInfo.td
View File

@ -190,7 +190,7 @@ def GR32 : RegisterClass<"SystemZ", [i32], 32,
GR32Class::iterator
GR32Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG32_nofp;
else
@ -199,7 +199,7 @@ def GR32 : RegisterClass<"SystemZ", [i32], 32,
GR32Class::iterator
GR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
else
@ -237,7 +237,7 @@ def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
ADDR32Class::iterator
ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_ADDR32_nofp;
else
@ -246,7 +246,7 @@ def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
ADDR32Class::iterator
ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
else
@ -284,7 +284,7 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64,
GR64Class::iterator
GR64Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG64_nofp;
else
@ -293,7 +293,7 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64,
GR64Class::iterator
GR64Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
else
@ -331,7 +331,7 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
ADDR64Class::iterator
ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_ADDR64_nofp;
else
@ -340,7 +340,7 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
ADDR64Class::iterator
ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
else
@ -368,7 +368,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
GR64PClass::iterator
GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG64P_nofp;
else
@ -377,7 +377,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
GR64PClass::iterator
GR64PClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
else
@ -405,7 +405,7 @@ def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
GR128Class::iterator
GR128Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG128_nofp;
else
@ -414,7 +414,7 @@ def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
GR128Class::iterator
GR128Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
if (TFI->hasFP(MF))
return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
else

2
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -30,7 +30,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T,
DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
"-f64:64:64-f128:128:128-a0:16:16-n32:64"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameInfo(Subtarget) {
FrameLowering(Subtarget) {
if (getRelocationModel() == Reloc::Default)
setRelocationModel(Reloc::Static);

10
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -17,12 +17,12 @@
#include "SystemZInstrInfo.h"
#include "SystemZISelLowering.h"
#include "SystemZFrameInfo.h"
#include "SystemZFrameLowering.h"
#include "SystemZSelectionDAGInfo.h"
#include "SystemZRegisterInfo.h"
#include "SystemZSubtarget.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -35,12 +35,14 @@ class SystemZTargetMachine : public LLVMTargetMachine {
SystemZInstrInfo InstrInfo;
SystemZTargetLowering TLInfo;
SystemZSelectionDAGInfo TSInfo;
SystemZFrameInfo FrameInfo;
SystemZFrameLowering FrameLowering;
public:
SystemZTargetMachine(const Target &T, const std::string &TT,
const std::string &FS);
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
}
virtual const SystemZInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetData *getTargetData() const { return &DataLayout;}
virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }

2
lib/Target/TargetAsmInfo.cpp
View File

@ -20,7 +20,7 @@ TargetAsmInfo::TargetAsmInfo(const TargetMachine &TM) {
const TargetData &TD = *TM.getTargetData();
IsLittleEndian = TD.isLittleEndian();
PointerSize = TD.getPointerSize();
const TargetFrameInfo &TFI = *TM.getFrameInfo();
const TargetFrameLowering &TFI = *TM.getFrameLowering();
StackDir = TFI.getStackGrowthDirection();
TRI = TM.getRegisterInfo();
TFI.getInitialFrameState(InitialFrameState);

15
lib/Target/TargetFrameInfo.cpp → lib/Target/TargetFrameLowering.cpp
View File

@ -1,4 +1,4 @@
//===-- TargetFrameInfo.cpp - Implement machine frame interface -*- C++ -*-===//
//===----- TargetFrameLowering.cpp - Implement target frame interface ------==//
//
// The LLVM Compiler Infrastructure
//
@ -13,35 +13,36 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdlib>
using namespace llvm;
TargetFrameInfo::~TargetFrameInfo() {
TargetFrameLowering::~TargetFrameLowering() {
}
/// getInitialFrameState - Returns a list of machine moves that are assumed
/// on entry to a function.
void
TargetFrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
TargetFrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves)
const {
// Default is to do nothing.
}
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index. This is the default implementation
/// which is overridden for some targets.
int TargetFrameInfo::getFrameIndexOffset(const MachineFunction &MF,
int TargetFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
int FI) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->getObjectOffset(FI) + MFI->getStackSize() -
getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
}
int TargetFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const {
int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF,
int FI, unsigned &FrameReg) const {
const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
// By default, assume all frame indices are referenced via whatever

1
lib/Target/TargetRegisterInfo.cpp
View File

@ -13,7 +13,6 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/ADT/BitVector.h"

32
lib/Target/X86/X86FrameInfo.cpp → lib/Target/X86/X86FrameLowering.cpp
View File

@ -1,4 +1,4 @@
//=======- X86FrameInfo.cpp - X86 Frame Information ------------*- C++ -*-====//
//=======- X86FrameLowering.cpp - X86 Frame Information ------------*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of TargetFrameInfo class.
// This file contains the X86 implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "X86FrameInfo.h"
#include "X86FrameLowering.h"
#include "X86InstrBuilder.h"
#include "X86InstrInfo.h"
#include "X86MachineFunctionInfo.h"
@ -32,14 +32,14 @@ using namespace llvm;
// FIXME: completely move here.
extern cl::opt<bool> ForceStackAlign;
bool X86FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo()->hasVarSizedObjects();
}
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
bool X86FrameInfo::hasFP(const MachineFunction &MF) const {
bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const MachineModuleInfo &MMI = MF.getMMI();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
@ -276,7 +276,7 @@ static bool isEAXLiveIn(MachineFunction &MF) {
return false;
}
void X86FrameInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
MCSymbol *Label,
unsigned FramePtr) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -292,8 +292,8 @@ void X86FrameInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
// Calculate amount of bytes used for return address storing.
int stackGrowth =
(TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ?
(TM.getFrameLowering()->getStackGrowthDirection() ==
TargetFrameLowering::StackGrowsUp ?
TD->getPointerSize() : -TD->getPointerSize());
// FIXME: This is dirty hack. The code itself is pretty mess right now.
@ -347,7 +347,7 @@ void X86FrameInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
/// space for local variables. Also emit labels used by the exception handler to
/// generate the exception handling frames.
void X86FrameInfo::emitPrologue(MachineFunction &MF) const {
void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -640,7 +640,7 @@ void X86FrameInfo::emitPrologue(MachineFunction &MF) const {
}
}
void X86FrameInfo::emitEpilogue(MachineFunction &MF,
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
@ -835,7 +835,7 @@ void X86FrameInfo::emitEpilogue(MachineFunction &MF,
}
void
X86FrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
X86FrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves) const {
// Calculate amount of bytes used for return address storing
int stackGrowth = (STI.is64Bit() ? -8 : -4);
const X86RegisterInfo *RI = TM.getRegisterInfo();
@ -851,7 +851,7 @@ X86FrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
Moves.push_back(MachineMove(0, CSDst, CSSrc));
}
int X86FrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
const X86RegisterInfo *RI =
static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
const MachineFrameInfo *MFI = MF.getFrameInfo();
@ -886,7 +886,7 @@ int X86FrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
return Offset;
}
bool X86FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -927,7 +927,7 @@ bool X86FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
}
bool X86FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
@ -958,7 +958,7 @@ bool X86FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
}
void
X86FrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
@ -984,7 +984,7 @@ X86FrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (hasFP(MF)) {
assert((TailCallReturnAddrDelta <= 0) &&
"The Delta should always be zero or negative");
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
// Create a frame entry for the EBP register that must be saved.
int FrameIdx = MFI->CreateFixedObject(SlotSize,

21
lib/Target/X86/X86FrameInfo.h → lib/Target/X86/X86FrameLowering.h
View File

@ -1,4 +1,4 @@
//===-- X86TargetFrameInfo.h - Define TargetFrameInfo for X86 ---*- C++ -*-===//
//=-- X86TargetFrameLowering.h - Define frame lowering for X86 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,28 +7,29 @@
//
//===----------------------------------------------------------------------===//
//
//
// This class implements X86-specific bits of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#ifndef X86_FRAMEINFO_H
#define X86_FRAMEINFO_H
#ifndef X86_FRAMELOWERING_H
#define X86_FRAMELOWERING_H
#include "X86Subtarget.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class MCSymbol;
class X86TargetMachine;
class X86FrameInfo : public TargetFrameInfo {
class X86FrameLowering : public TargetFrameLowering {
const X86TargetMachine &TM;
const X86Subtarget &STI;
public:
explicit X86FrameInfo(const X86TargetMachine &tm, const X86Subtarget &sti)
: TargetFrameInfo(StackGrowsDown,
sti.getStackAlignment(),
(sti.isTargetWin64() ? -40 : (sti.is64Bit() ? -8 : -4))),
explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
: TargetFrameLowering(StackGrowsDown,
sti.getStackAlignment(),
(sti.isTargetWin64() ? -40 :
(sti.is64Bit() ? -8 : -4))),
TM(tm), STI(sti) {
}

10
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1145,6 +1145,7 @@ unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
}
// FIXME: Why this routine is here? Move to RegInfo!
std::pair<const TargetRegisterClass*, uint8_t>
X86TargetLowering::findRepresentativeClass(EVT VT) const{
const TargetRegisterClass *RRC = 0;
@ -1170,10 +1171,11 @@ X86TargetLowering::findRepresentativeClass(EVT VT) const{
return std::make_pair(RRC, Cost);
}
// FIXME: Why this routine is here? Move to RegInfo!
unsigned
X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
switch (RC->getID()) {
@ -1704,7 +1706,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
TotalNumXMMRegs = 0;
if (IsWin64) {
const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
// Get to the caller-allocated home save location. Add 8 to account
// for the return address.
int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
@ -2296,7 +2298,7 @@ X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
SelectionDAG& DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo &TFI = *TM.getFrameInfo();
const TargetFrameLowering &TFI = *TM.getFrameLowering();
unsigned StackAlignment = TFI.getStackAlignment();
uint64_t AlignMask = StackAlignment - 1;
int64_t Offset = StackSize;
@ -8216,7 +8218,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
MachineFunction &MF = DAG.getMachineFunction();
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo &TFI = *TM.getFrameInfo();
const TargetFrameLowering &TFI = *TM.getFrameLowering();
unsigned StackAlignment = TFI.getStackAlignment();
EVT VT = Op.getValueType();
DebugLoc DL = Op.getDebugLoc();

14
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -31,7 +31,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@ -60,7 +60,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
Is64Bit = Subtarget->is64Bit();
IsWin64 = Subtarget->isTargetWin64();
StackAlign = TM.getFrameInfo()->getStackAlignment();
StackAlign = TM.getFrameLowering()->getStackAlignment();
if (Is64Bit) {
SlotSize = 8;
@ -388,7 +388,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
// Set the stack-pointer register and its aliases as reserved.
Reserved.set(X86::RSP);
@ -455,7 +455,7 @@ bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
unsigned Reg, int &FrameIdx) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (Reg == FramePtr && TFI->hasFP(MF)) {
FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
@ -491,7 +491,7 @@ static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
void X86RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
int Opcode = I->getOpcode();
bool isDestroy = Opcode == getCallFrameDestroyOpcode();
@ -565,7 +565,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned i = 0;
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
while (!MI.getOperand(i).isFI()) {
++i;
@ -614,7 +614,7 @@ unsigned X86RegisterInfo::getRARegister() const {
}
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return TFI->hasFP(MF) ? FramePtr : StackPtr;
}

20
lib/Target/X86/X86RegisterInfo.td
View File

@ -299,7 +299,7 @@ def GR8 : RegisterClass<"X86", [i8], 8,
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP / EBP to being a frame ptr?
@ -344,7 +344,7 @@ def GR16 : RegisterClass<"X86", [i16], 16,
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
if (Subtarget.is64Bit()) {
@ -396,7 +396,7 @@ def GR32 : RegisterClass<"X86", [i32], 32,
GR32Class::iterator
GR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
if (Subtarget.is64Bit()) {
@ -436,7 +436,7 @@ def GR64 : RegisterClass<"X86", [i64], 64,
GR64Class::iterator
GR64Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
if (!Subtarget.is64Bit())
@ -541,7 +541,7 @@ def GR16_NOREX : RegisterClass<"X86", [i16], 16,
GR16_NOREXClass::iterator
GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP / EBP to being a frame ptr?
if (TFI->hasFP(MF) || MFI->getReserveFP())
@ -565,7 +565,7 @@ def GR32_NOREX : RegisterClass<"X86", [i32], 32,
GR32_NOREXClass::iterator
GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP / EBP to being a frame ptr?
if (TFI->hasFP(MF) || MFI->getReserveFP())
@ -590,7 +590,7 @@ def GR64_NOREX : RegisterClass<"X86", [i64], 64,
GR64_NOREXClass::iterator
GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP to being a frame ptr?
if (TFI->hasFP(MF) || MFI->getReserveFP())
@ -632,7 +632,7 @@ def GR32_NOSP : RegisterClass<"X86", [i32], 32,
GR32_NOSPClass::iterator
GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
if (Subtarget.is64Bit()) {
@ -670,7 +670,7 @@ def GR64_NOSP : RegisterClass<"X86", [i64], 64,
GR64_NOSPClass::iterator
GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
if (!Subtarget.is64Bit())
@ -698,7 +698,7 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
{
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo *TFI = TM.getFrameInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP to being a frame ptr?
if (TFI->hasFP(MF) || MFI->getReserveFP())

2
lib/Target/X86/X86TargetMachine.cpp
View File

@ -119,7 +119,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
const std::string &FS, bool is64Bit)
: LLVMTargetMachine(T, TT),
Subtarget(TT, FS, is64Bit),
FrameInfo(*this, Subtarget),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
DefRelocModel = getRelocationModel();

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