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* Removed extraneous #includes

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* Fixed file headers to be consistent with the rest of LLVM
* Other minor fixes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-08-09 20:08:03 +00:00
parent b91b31c12d
commit 179cdfb5c8
16 changed files with 77 additions and 176 deletions
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11
include/llvm/CodeGen/InstrForest.h
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@ -1,8 +1,5 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// InstrForest.h
//
//===-- llvm/CodeGen/InstForest.h ------------------------------*- C++ -*--===//
//
// Purpose:
// Convert SSA graph to instruction trees for instruction selection.
//
@ -17,9 +14,7 @@
// (2) O and I are part of the same basic block, and
// (3) O has only a single use, viz., I.
//
// History:
// 6/28/01 - Vikram Adve - Created
//**************************************************************************/
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_INSTRFOREST_H
#define LLVM_CODEGEN_INSTRFOREST_H

22
include/llvm/CodeGen/InstrSelection.h
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@ -1,14 +1,8 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// InstrSelection.h
//
// Purpose:
// External interface to instruction selection.
//
// History:
// 7/02/01 - Vikram Adve - Created
//**************************************************************************/
//===-- llvm/CodeGen/InstrSelection.h --------------------------*- C++ -*--===//
//
// External interface to instruction selection.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_INSTR_SELECTION_H
#define LLVM_CODEGEN_INSTR_SELECTION_H
@ -21,9 +15,9 @@ class InstructionNode;
class TargetMachine;
class Pass;
/************************* Required Functions *******************************
* Target-dependent functions that MUST be implemented for each target.
***************************************************************************/
//===--------------------- Required Functions ---------------------------------
// Target-dependent functions that MUST be implemented for each target.
//
const unsigned MAX_INSTR_PER_VMINSTR = 8;

16
include/llvm/CodeGen/InstrSelectionSupport.h
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@ -1,15 +1,9 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// InstrSelectionSupport.h
//
// Purpose:
// Target-independent instruction selection code.
// See SparcInstrSelection.cpp for usage.
//===-- llvm/CodeGen/InstrSelectionSupport.h --------------------*- C++ -*-===//
//
// Target-independent instruction selection code. See SparcInstrSelection.cpp
// for usage.
//
// History:
// 10/10/01 - Vikram Adve - Created
//**************************************************************************/
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H
#define LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H

20
include/llvm/CodeGen/MachineInstrAnnot.h
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@ -1,29 +1,20 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// MachineInstrAnnot.h
//===-- llvm/CodeGen/MachineInstrAnnot.h ------------------------*- C++ -*-===//
//
// Annotations used to pass information between code generation phases.
//
// Purpose:
// Annotations used to pass information between code generation phases.
//
// History:
// 5/10/02 - Vikram Adve - Created
//**************************************************************************/
//===----------------------------------------------------------------------===//
#ifndef MACHINE_INSTR_ANNOT_h
#define MACHINE_INSTR_ANNOT_h
#include "llvm/Annotation.h"
#include "llvm/CodeGen/MachineInstr.h"
#include <vector>
class Value;
class TmpInstruction;
class CallInst;
class CallArgInfo {
private:
// Flag values for different argument passing methods
static const unsigned char IntArgReg = 0x1;
static const unsigned char FPArgReg = 0x2;
@ -60,9 +51,8 @@ public:
class CallArgsDescriptor: public Annotation { // Annotation for a MachineInstr
private:
static AnnotationID AID; // AnnotationID for this class
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
const CallInst* callInstr; // The call instruction == result value
const Value* funcPtr; // Pointer for indirect calls
TmpInstruction* retAddrReg; // Tmp value for return address reg.

1
lib/CodeGen/InstrSched/InstrScheduling.cpp
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@ -13,7 +13,6 @@
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
#include "llvm/Instruction.h"
#include "Support/CommandLine.h"
#include <algorithm>
using std::cerr;

29
lib/CodeGen/InstrSched/SchedGraph.h
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@ -1,20 +1,15 @@
/* -*-C++-*-
****************************************************************************
* File:
* SchedGraph.h
*
* Purpose:
* Scheduling graph based on SSA graph plus extra dependence edges
* capturing dependences due to machine resources (machine registers,
* CC registers, and any others).
*
* Strategy:
* This graph tries to leverage the SSA graph as much as possible,
* but captures the extra dependences through a common interface.
*
* History:
* 7/20/01 - Vikram Adve - Created
***************************************************************************/
//===-- SchedGraph.h - Scheduling Graph --------------------------*- C++ -*--=//
//
// Purpose:
// Scheduling graph based on SSA graph plus extra dependence edges
// capturing dependences due to machine resources (machine registers,
// CC registers, and any others).
//
// Strategy:
// This graph tries to leverage the SSA graph as much as possible,
// but captures the extra dependences through a common interface.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDGRAPH_H
#define LLVM_CODEGEN_SCHEDGRAPH_H

14
lib/CodeGen/InstrSched/SchedPriorities.cpp
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@ -1,10 +1,4 @@
// $Id$ -*-C++-*-
//***************************************************************************
// File:
// SchedPriorities.h
//
// Purpose:
// Encapsulate heuristics for instruction scheduling.
//===-- SchedPriorities.h - Encapsulate scheduling heuristics -------------===//
//
// Strategy:
// Priority ordering rules:
@ -13,10 +7,8 @@
// (3) Instruction that has the maximum number of dependent instructions.
// Note that rules 2 and 3 are only used if issue conflicts prevent
// choosing a higher priority instruction by rule 1.
//
// History:
// 7/30/01 - Vikram Adve - Created
//**************************************************************************/
//
//===----------------------------------------------------------------------===//
#include "SchedPriorities.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"

16
lib/CodeGen/InstrSched/SchedPriorities.h
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@ -1,10 +1,4 @@
// -*-C++-*-
//***************************************************************************
// File:
// SchedPriorities.h
//
// Purpose:
// Encapsulate heuristics for instruction scheduling.
//===-- SchedPriorities.h - Encapsulate scheduling heuristics --*- C++ -*--===//
//
// Strategy:
// Priority ordering rules:
@ -13,10 +7,8 @@
// (3) Instruction that has the maximum number of dependent instructions.
// Note that rules 2 and 3 are only used if issue conflicts prevent
// choosing a higher priority instruction by rule 1.
//
// History:
// 7/30/01 - Vikram Adve - Created
//**************************************************************************/
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDPRIORITIES_H
#define LLVM_CODEGEN_SCHEDPRIORITIES_H
@ -26,7 +18,7 @@
#include "llvm/Target/MachineSchedInfo.h"
#include <list>
#include <Support/hash_set>
#include <iostream>
class Function;
class MachineInstr;
class SchedulingManager;

13
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
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@ -1,13 +1,8 @@
//***************************************************************************
// File:
// PhyRegAlloc.cpp
//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
//
// Purpose:
// Register allocation for LLVM.
//
// History:
// 9/10/01 - Ruchira Sasanka - created.
//**************************************************************************/
// Register allocation for LLVM.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/PhyRegAlloc.h"

18
lib/Target/MachineFrameInfo.cpp
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@ -1,22 +1,14 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// MachineFrameInfo.cpp
//===-- MachineFrameInfo.cpp-----------------------------------------------===//
//
// Purpose:
// Interface to layout of stack frame on target machine.
// Most functions of class MachineFrameInfo have to be machine-specific
// so there is little code here.
// Interface to layout of stack frame on target machine. Most functions of
// class MachineFrameInfo have to be machine-specific so there is little code
// here.
//
// History:
// 4/17/02 - Vikram Adve - Created
//**************************************************************************/
//===----------------------------------------------------------------------===//
#include "llvm/Target/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
int
MachineFrameInfo::getIncomingArgOffset(MachineCodeForMethod& mcInfo,
unsigned argNum) const

1
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
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@ -13,7 +13,6 @@
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
#include "llvm/Instruction.h"
#include "Support/CommandLine.h"
#include <algorithm>
using std::cerr;

29
lib/Target/SparcV9/InstrSched/SchedGraph.h
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@ -1,20 +1,15 @@
/* -*-C++-*-
****************************************************************************
* File:
* SchedGraph.h
*
* Purpose:
* Scheduling graph based on SSA graph plus extra dependence edges
* capturing dependences due to machine resources (machine registers,
* CC registers, and any others).
*
* Strategy:
* This graph tries to leverage the SSA graph as much as possible,
* but captures the extra dependences through a common interface.
*
* History:
* 7/20/01 - Vikram Adve - Created
***************************************************************************/
//===-- SchedGraph.h - Scheduling Graph --------------------------*- C++ -*--=//
//
// Purpose:
// Scheduling graph based on SSA graph plus extra dependence edges
// capturing dependences due to machine resources (machine registers,
// CC registers, and any others).
//
// Strategy:
// This graph tries to leverage the SSA graph as much as possible,
// but captures the extra dependences through a common interface.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDGRAPH_H
#define LLVM_CODEGEN_SCHEDGRAPH_H

14
lib/Target/SparcV9/InstrSched/SchedPriorities.cpp
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@ -1,10 +1,4 @@
// $Id$ -*-C++-*-
//***************************************************************************
// File:
// SchedPriorities.h
//
// Purpose:
// Encapsulate heuristics for instruction scheduling.
//===-- SchedPriorities.h - Encapsulate scheduling heuristics -------------===//
//
// Strategy:
// Priority ordering rules:
@ -13,10 +7,8 @@
// (3) Instruction that has the maximum number of dependent instructions.
// Note that rules 2 and 3 are only used if issue conflicts prevent
// choosing a higher priority instruction by rule 1.
//
// History:
// 7/30/01 - Vikram Adve - Created
//**************************************************************************/
//
//===----------------------------------------------------------------------===//
#include "SchedPriorities.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"

16
lib/Target/SparcV9/InstrSched/SchedPriorities.h
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@ -1,10 +1,4 @@
// -*-C++-*-
//***************************************************************************
// File:
// SchedPriorities.h
//
// Purpose:
// Encapsulate heuristics for instruction scheduling.
//===-- SchedPriorities.h - Encapsulate scheduling heuristics --*- C++ -*--===//
//
// Strategy:
// Priority ordering rules:
@ -13,10 +7,8 @@
// (3) Instruction that has the maximum number of dependent instructions.
// Note that rules 2 and 3 are only used if issue conflicts prevent
// choosing a higher priority instruction by rule 1.
//
// History:
// 7/30/01 - Vikram Adve - Created
//**************************************************************************/
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDPRIORITIES_H
#define LLVM_CODEGEN_SCHEDPRIORITIES_H
@ -26,7 +18,7 @@
#include "llvm/Target/MachineSchedInfo.h"
#include <list>
#include <Support/hash_set>
#include <iostream>
class Function;
class MachineInstr;
class SchedulingManager;

20
lib/Target/SparcV9/MachineInstrAnnot.h
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@ -1,29 +1,20 @@
// $Id$ -*-c++-*-
//***************************************************************************
// File:
// MachineInstrAnnot.h
//===-- llvm/CodeGen/MachineInstrAnnot.h ------------------------*- C++ -*-===//
//
// Annotations used to pass information between code generation phases.
//
// Purpose:
// Annotations used to pass information between code generation phases.
//
// History:
// 5/10/02 - Vikram Adve - Created
//**************************************************************************/
//===----------------------------------------------------------------------===//
#ifndef MACHINE_INSTR_ANNOT_h
#define MACHINE_INSTR_ANNOT_h
#include "llvm/Annotation.h"
#include "llvm/CodeGen/MachineInstr.h"
#include <vector>
class Value;
class TmpInstruction;
class CallInst;
class CallArgInfo {
private:
// Flag values for different argument passing methods
static const unsigned char IntArgReg = 0x1;
static const unsigned char FPArgReg = 0x2;
@ -60,9 +51,8 @@ public:
class CallArgsDescriptor: public Annotation { // Annotation for a MachineInstr
private:
static AnnotationID AID; // AnnotationID for this class
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
const CallInst* callInstr; // The call instruction == result value
const Value* funcPtr; // Pointer for indirect calls
TmpInstruction* retAddrReg; // Tmp value for return address reg.

13
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
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@ -1,13 +1,8 @@
//***************************************************************************
// File:
// PhyRegAlloc.cpp
//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
//
// Purpose:
// Register allocation for LLVM.
//
// History:
// 9/10/01 - Ruchira Sasanka - created.
//**************************************************************************/
// Register allocation for LLVM.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/PhyRegAlloc.h"