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Fix these test cases to not use .bc files. Otherwise, we run into issues with

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bitcode reader/writer backward compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-10-25 01:22:20 +00:00
parent f2a783303e
commit 17d47e423d
4 changed files with 97 additions and 2 deletions
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17
test/Bitcode/sse42_crc32.ll
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@ -3,7 +3,7 @@
;
; Rdar: 9472944
;
; RUN: llvm-dis < %s.bc | FileCheck %s
; RUN: opt < %s | llvm-dis | FileCheck %s
; crc32.8 should upgrade to crc32.32.8
; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
@ -26,3 +26,18 @@
; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
define void @foo() nounwind readnone ssp {
entry:
%0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
%1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
%2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
%3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
%4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
ret void
}
declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone

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test/Bitcode/sse42_crc32.ll.bc
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82
test/Bitcode/ssse3_palignr.ll
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@ -1,2 +1,82 @@
; RUN: llvm-dis < %s.bc | FileCheck %s
; RUN: opt < %s | llvm-dis | FileCheck %s
; CHECK-NOT: {@llvm\\.palign}
define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
%1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
ret <4 x i32> %3
}
define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
%1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
%3 = extractelement <1 x i64> %2, i32 0 ; <i64> [#uses=1]
%retval12 = bitcast i64 %3 to double ; <double> [#uses=1]
ret double %retval12
}
declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
%1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
%3 = extractelement <1 x i64> %2, i32 0 ; <i64> [#uses=1]
%retval12 = bitcast i64 %3 to double ; <double> [#uses=1]
ret double %retval12
}
define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
%1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
%3 = extractelement <1 x i64> %2, i32 0 ; <i64> [#uses=1]
%retval12 = bitcast i64 %3 to double ; <double> [#uses=1]
ret double %retval12
}
define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
%1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
%3 = extractelement <1 x i64> %2, i32 0 ; <i64> [#uses=1]
%retval12 = bitcast i64 %3 to double ; <double> [#uses=1]
ret double %retval12
}
define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
%1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
ret <4 x i32> %3
}
declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
%1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
ret <4 x i32> %3
}
define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
entry:
%0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
%1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
ret <4 x i32> %3
}

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test/Bitcode/ssse3_palignr.ll.bc
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