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[C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202607 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -41,7 +41,7 @@ template <typename PointerTy, unsigned IntBits, typename IntType=unsigned,
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typename PtrTraits = PointerLikeTypeTraits<PointerTy> >
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class PointerIntPair {
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intptr_t Value;
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enum LLVM_ENUM_INT_TYPE(uintptr_t) {
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enum : uintptr_t {
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/// PointerBitMask - The bits that come from the pointer.
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PointerBitMask =
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~(uintptr_t)(((intptr_t)1 << PtrTraits::NumLowBitsAvailable)-1),
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@ -254,7 +254,7 @@ namespace llvm {
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/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
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class SUnit {
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private:
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enum LLVM_ENUM_INT_TYPE(unsigned) { BoundaryID = ~0u };
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enum : unsigned { BoundaryID = ~0u };
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SDNode *Node; // Representative node.
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MachineInstr *Instr; // Alternatively, a MachineInstr.
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@ -202,7 +202,7 @@ public:
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/// index `1'.
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class AttributeSet {
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public:
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enum AttrIndex LLVM_ENUM_INT_TYPE(unsigned) {
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enum AttrIndex : unsigned {
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ReturnIndex = 0U,
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FunctionIndex = ~0U
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};
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@ -197,7 +197,7 @@ public:
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// These are helper methods for dealing with flags in the INLINEASM SDNode
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// in the backend.
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Fixed operands on an INLINEASM SDNode.
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Op_InputChain = 0,
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Op_AsmString = 1,
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@ -28,7 +28,7 @@ template<typename ValueSubClass, typename ItemParentClass>
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class SymbolTableListTraits;
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enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
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enum LLVMConstants : uint32_t {
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DEBUG_METADATA_VERSION = 1 // Current debug info version number.
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};
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@ -41,7 +41,7 @@ public:
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/// These are the section type and attributes fields. A MachO section can
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/// have only one Type, but can have any of the attributes specified.
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// TypeAndAttributes bitmasks.
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SECTION_TYPE = 0x000000FFU,
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SECTION_ATTRIBUTES = 0xFFFFFF00U,
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@ -28,7 +28,7 @@ private:
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unsigned Register; // gcc/gdb register number.
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int Offset; // Displacement if not register.
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public:
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// The target register number for an abstract frame pointer. The value is
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// an arbitrary value that doesn't collide with any real target register.
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VirtualFP = ~0U
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@ -75,7 +75,7 @@ class BasicSymbolRef {
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public:
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// FIXME: should we add a SF_Text?
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enum Flags LLVM_ENUM_INT_TYPE(unsigned) {
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enum Flags : unsigned {
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SF_None = 0,
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SF_Undefined = 1U << 0, // Symbol is defined in another object file
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SF_Global = 1U << 1, // Global symbol
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@ -222,7 +222,7 @@ namespace COFF {
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uint32_t Characteristics;
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};
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enum SectionCharacteristics LLVM_ENUM_INT_TYPE(uint32_t) {
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enum SectionCharacteristics : uint32_t {
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SC_Invalid = 0xffffffff,
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IMAGE_SCN_TYPE_NO_PAD = 0x00000008,
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@ -365,24 +365,6 @@
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# define LLVM_STATIC_ASSERT(expr, msg)
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#endif
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/// \macro LLVM_ENUM_INT_TYPE
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/// \brief Expands to colon followed by the given integral type on compilers
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/// which support C++11 strong enums. This can be used to make enums unsigned
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/// with MSVC.
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#if __has_feature(cxx_strong_enums) || LLVM_MSC_PREREQ(1600)
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# define LLVM_ENUM_INT_TYPE(intty) : intty
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#else
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# define LLVM_ENUM_INT_TYPE(intty)
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#endif
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/// \brief Does the compiler support C++11 semantics for strongly typed forward
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/// declared enums?
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#if __has_feature(cxx_strong_enums) || LLVM_MSC_PREREQ(1700)
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#define LLVM_HAS_STRONG_ENUMS 1
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#else
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#define LLVM_HAS_STRONG_ENUMS 0
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#endif
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/// \brief Does the compiler support generalized initializers (using braced
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/// lists and std::initializer_list). While clang may claim it supports general
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/// initializers, if we're using MSVC's headers, we might not have a usable
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@ -24,7 +24,7 @@ namespace llvm {
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//===----------------------------------------------------------------------===//
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// Debug info constants.
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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LLVMDebugVersion = (12 << 16), // Current version of debug information.
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LLVMDebugVersion11 = (11 << 16), // Constant for version 11.
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LLVMDebugVersion10 = (10 << 16), // Constant for version 10.
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@ -47,7 +47,7 @@ namespace dwarf {
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// Do not mix the following two enumerations sets. DW_TAG_invalid changes the
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// enumeration base type.
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enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
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enum LLVMConstants : uint32_t {
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// llvm mock tags
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DW_TAG_invalid = ~0U, // Tag for invalid results.
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@ -68,7 +68,7 @@ enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
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const uint32_t DW_CIE_ID = UINT32_MAX;
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const uint64_t DW64_CIE_ID = UINT64_MAX;
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enum Tag LLVM_ENUM_INT_TYPE(uint16_t) {
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enum Tag : uint16_t {
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DW_TAG_array_type = 0x01,
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DW_TAG_class_type = 0x02,
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DW_TAG_entry_point = 0x03,
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@ -175,7 +175,7 @@ inline bool isType(Tag T) {
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}
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}
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enum Attribute LLVM_ENUM_INT_TYPE(uint16_t) {
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enum Attribute : uint16_t {
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// Attributes
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DW_AT_sibling = 0x01,
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DW_AT_location = 0x02,
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@ -341,7 +341,7 @@ enum Attribute LLVM_ENUM_INT_TYPE(uint16_t) {
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DW_AT_APPLE_property = 0x3fed
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};
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enum Form LLVM_ENUM_INT_TYPE(uint16_t) {
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enum Form : uint16_t {
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// Attribute form encodings
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DW_FORM_addr = 0x01,
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DW_FORM_block2 = 0x03,
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@ -651,7 +651,7 @@ enum {
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};
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// ARM Specific e_flags
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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EF_ARM_SOFT_FLOAT = 0x00000200U,
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EF_ARM_VFP_FLOAT = 0x00000400U,
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EF_ARM_EABI_UNKNOWN = 0x00000000U,
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@ -801,7 +801,7 @@ enum {
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};
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// Mips Specific e_flags
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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EF_MIPS_NOREORDER = 0x00000001, // Don't reorder instructions
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EF_MIPS_PIC = 0x00000002, // Position independent code
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EF_MIPS_CPIC = 0x00000004, // Call object with Position independent code
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@ -1222,7 +1222,7 @@ enum {
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};
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// Section types.
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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SHT_NULL = 0, // No associated section (inactive entry).
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SHT_PROGBITS = 1, // Program-defined contents.
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SHT_SYMTAB = 2, // Symbol table.
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@ -1270,7 +1270,7 @@ enum LLVM_ENUM_INT_TYPE(unsigned) {
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};
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// Section flags.
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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// Section data should be writable during execution.
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SHF_WRITE = 0x1,
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@ -1362,7 +1362,7 @@ enum LLVM_ENUM_INT_TYPE(unsigned) {
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};
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// Section Group Flags
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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GRP_COMDAT = 0x1,
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GRP_MASKOS = 0x0ff00000,
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GRP_MASKPROC = 0xf0000000
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@ -1584,7 +1584,7 @@ enum {
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};
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// Segment flag bits.
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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PF_X = 1, // Execute
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PF_W = 2, // Write
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PF_R = 4, // Read
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@ -21,7 +21,7 @@
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namespace llvm {
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namespace MachO {
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// Enums from <mach-o/loader.h>
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Constants for the "magic" field in llvm::MachO::mach_header and
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// llvm::MachO::mach_header_64
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MH_MAGIC = 0xFEEDFACEu,
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@ -76,12 +76,12 @@ namespace llvm {
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MH_DEAD_STRIPPABLE_DYLIB = 0x00400000u
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};
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Flags for the "cmd" field in llvm::MachO::load_command
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LC_REQ_DYLD = 0x80000000u
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};
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enum LoadCommandType LLVM_ENUM_INT_TYPE(uint32_t) {
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enum LoadCommandType : uint32_t {
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// Constants for the "cmd" field in llvm::MachO::load_command
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LC_SEGMENT = 0x00000001u,
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LC_SYMTAB = 0x00000002u,
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@ -131,7 +131,7 @@ namespace llvm {
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LC_LINKER_OPTIONS = 0x0000002Du
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};
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Constant bits for the "flags" field in llvm::MachO::segment_command
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SG_HIGHVM = 0x1u,
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SG_FVMLIB = 0x2u,
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@ -174,7 +174,7 @@ namespace llvm {
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S_THREAD_LOCAL_INIT_FUNCTION_POINTERS = 0x15u
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};
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Constant masks for the "flags[31:24]" field in llvm::MachO::section and
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// llvm::MachO::section_64 (mask "flags" with SECTION_ATTRIBUTES_USR)
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S_ATTR_PURE_INSTRUCTIONS = 0x80000000u,
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@ -348,7 +348,7 @@ namespace llvm {
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N_LENG = 0xFEu
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};
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Constant values for the r_symbolnum field in an
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// llvm::MachO::relocation_info structure when r_extern is 0.
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R_ABS = 0,
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@ -893,7 +893,7 @@ namespace llvm {
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}
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// Enums from <mach/machine.h>
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Capability bits used in the definition of cpu_type.
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CPU_ARCH_MASK = 0xff000000, // Mask for architecture bits
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CPU_ARCH_ABI64 = 0x01000000 // 64 bit ABI
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@ -913,7 +913,7 @@ namespace llvm {
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CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
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};
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enum LLVM_ENUM_INT_TYPE(uint32_t) {
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enum : uint32_t {
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// Capability bits used in the definition of cpusubtype.
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CPU_SUB_TYPE_MASK = 0xff000000, // Mask for architecture bits
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CPU_SUB_TYPE_LIB64 = 0x80000000, // 64 bit libraries
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// not be erased.
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bool isBulkSpilling;
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enum LLVM_ENUM_INT_TYPE(unsigned) {
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enum : unsigned {
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spillClean = 1,
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spillDirty = 100,
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spillImpossible = ~0u
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/// class.
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SmallVector<GlobalSplitCandidate, 32> GlobalCand;
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enum LLVM_ENUM_INT_TYPE(unsigned) { NoCand = ~0u };
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enum : unsigned { NoCand = ~0u };
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/// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
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/// NoCand which indicates the stack interval.
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