[C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macro

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alp Toker 2014-03-02 03:20:38 +00:00
parent 243491693b
commit 18510b7e43
15 changed files with 30 additions and 48 deletions

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@ -41,7 +41,7 @@ template <typename PointerTy, unsigned IntBits, typename IntType=unsigned,
typename PtrTraits = PointerLikeTypeTraits<PointerTy> >
class PointerIntPair {
intptr_t Value;
enum LLVM_ENUM_INT_TYPE(uintptr_t) {
enum : uintptr_t {
/// PointerBitMask - The bits that come from the pointer.
PointerBitMask =
~(uintptr_t)(((intptr_t)1 << PtrTraits::NumLowBitsAvailable)-1),

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@ -254,7 +254,7 @@ namespace llvm {
/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
class SUnit {
private:
enum LLVM_ENUM_INT_TYPE(unsigned) { BoundaryID = ~0u };
enum : unsigned { BoundaryID = ~0u };
SDNode *Node; // Representative node.
MachineInstr *Instr; // Alternatively, a MachineInstr.

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@ -202,7 +202,7 @@ public:
/// index `1'.
class AttributeSet {
public:
enum AttrIndex LLVM_ENUM_INT_TYPE(unsigned) {
enum AttrIndex : unsigned {
ReturnIndex = 0U,
FunctionIndex = ~0U
};

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@ -197,7 +197,7 @@ public:
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Fixed operands on an INLINEASM SDNode.
Op_InputChain = 0,
Op_AsmString = 1,

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@ -28,7 +28,7 @@ template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits;
enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
enum LLVMConstants : uint32_t {
DEBUG_METADATA_VERSION = 1 // Current debug info version number.
};

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@ -41,7 +41,7 @@ public:
/// These are the section type and attributes fields. A MachO section can
/// have only one Type, but can have any of the attributes specified.
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// TypeAndAttributes bitmasks.
SECTION_TYPE = 0x000000FFU,
SECTION_ATTRIBUTES = 0xFFFFFF00U,

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@ -28,7 +28,7 @@ private:
unsigned Register; // gcc/gdb register number.
int Offset; // Displacement if not register.
public:
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// The target register number for an abstract frame pointer. The value is
// an arbitrary value that doesn't collide with any real target register.
VirtualFP = ~0U

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@ -75,7 +75,7 @@ class BasicSymbolRef {
public:
// FIXME: should we add a SF_Text?
enum Flags LLVM_ENUM_INT_TYPE(unsigned) {
enum Flags : unsigned {
SF_None = 0,
SF_Undefined = 1U << 0, // Symbol is defined in another object file
SF_Global = 1U << 1, // Global symbol

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@ -222,7 +222,7 @@ namespace COFF {
uint32_t Characteristics;
};
enum SectionCharacteristics LLVM_ENUM_INT_TYPE(uint32_t) {
enum SectionCharacteristics : uint32_t {
SC_Invalid = 0xffffffff,
IMAGE_SCN_TYPE_NO_PAD = 0x00000008,

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@ -365,24 +365,6 @@
# define LLVM_STATIC_ASSERT(expr, msg)
#endif
/// \macro LLVM_ENUM_INT_TYPE
/// \brief Expands to colon followed by the given integral type on compilers
/// which support C++11 strong enums. This can be used to make enums unsigned
/// with MSVC.
#if __has_feature(cxx_strong_enums) || LLVM_MSC_PREREQ(1600)
# define LLVM_ENUM_INT_TYPE(intty) : intty
#else
# define LLVM_ENUM_INT_TYPE(intty)
#endif
/// \brief Does the compiler support C++11 semantics for strongly typed forward
/// declared enums?
#if __has_feature(cxx_strong_enums) || LLVM_MSC_PREREQ(1700)
#define LLVM_HAS_STRONG_ENUMS 1
#else
#define LLVM_HAS_STRONG_ENUMS 0
#endif
/// \brief Does the compiler support generalized initializers (using braced
/// lists and std::initializer_list). While clang may claim it supports general
/// initializers, if we're using MSVC's headers, we might not have a usable

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@ -24,7 +24,7 @@ namespace llvm {
//===----------------------------------------------------------------------===//
// Debug info constants.
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
LLVMDebugVersion = (12 << 16), // Current version of debug information.
LLVMDebugVersion11 = (11 << 16), // Constant for version 11.
LLVMDebugVersion10 = (10 << 16), // Constant for version 10.
@ -47,7 +47,7 @@ namespace dwarf {
// Do not mix the following two enumerations sets. DW_TAG_invalid changes the
// enumeration base type.
enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
enum LLVMConstants : uint32_t {
// llvm mock tags
DW_TAG_invalid = ~0U, // Tag for invalid results.
@ -68,7 +68,7 @@ enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
const uint32_t DW_CIE_ID = UINT32_MAX;
const uint64_t DW64_CIE_ID = UINT64_MAX;
enum Tag LLVM_ENUM_INT_TYPE(uint16_t) {
enum Tag : uint16_t {
DW_TAG_array_type = 0x01,
DW_TAG_class_type = 0x02,
DW_TAG_entry_point = 0x03,
@ -175,7 +175,7 @@ inline bool isType(Tag T) {
}
}
enum Attribute LLVM_ENUM_INT_TYPE(uint16_t) {
enum Attribute : uint16_t {
// Attributes
DW_AT_sibling = 0x01,
DW_AT_location = 0x02,
@ -341,7 +341,7 @@ enum Attribute LLVM_ENUM_INT_TYPE(uint16_t) {
DW_AT_APPLE_property = 0x3fed
};
enum Form LLVM_ENUM_INT_TYPE(uint16_t) {
enum Form : uint16_t {
// Attribute form encodings
DW_FORM_addr = 0x01,
DW_FORM_block2 = 0x03,

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@ -651,7 +651,7 @@ enum {
};
// ARM Specific e_flags
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
EF_ARM_SOFT_FLOAT = 0x00000200U,
EF_ARM_VFP_FLOAT = 0x00000400U,
EF_ARM_EABI_UNKNOWN = 0x00000000U,
@ -801,7 +801,7 @@ enum {
};
// Mips Specific e_flags
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
EF_MIPS_NOREORDER = 0x00000001, // Don't reorder instructions
EF_MIPS_PIC = 0x00000002, // Position independent code
EF_MIPS_CPIC = 0x00000004, // Call object with Position independent code
@ -1222,7 +1222,7 @@ enum {
};
// Section types.
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
SHT_NULL = 0, // No associated section (inactive entry).
SHT_PROGBITS = 1, // Program-defined contents.
SHT_SYMTAB = 2, // Symbol table.
@ -1270,7 +1270,7 @@ enum LLVM_ENUM_INT_TYPE(unsigned) {
};
// Section flags.
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
// Section data should be writable during execution.
SHF_WRITE = 0x1,
@ -1362,7 +1362,7 @@ enum LLVM_ENUM_INT_TYPE(unsigned) {
};
// Section Group Flags
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
GRP_COMDAT = 0x1,
GRP_MASKOS = 0x0ff00000,
GRP_MASKPROC = 0xf0000000
@ -1584,7 +1584,7 @@ enum {
};
// Segment flag bits.
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
PF_X = 1, // Execute
PF_W = 2, // Write
PF_R = 4, // Read

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@ -21,7 +21,7 @@
namespace llvm {
namespace MachO {
// Enums from <mach-o/loader.h>
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Constants for the "magic" field in llvm::MachO::mach_header and
// llvm::MachO::mach_header_64
MH_MAGIC = 0xFEEDFACEu,
@ -76,12 +76,12 @@ namespace llvm {
MH_DEAD_STRIPPABLE_DYLIB = 0x00400000u
};
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Flags for the "cmd" field in llvm::MachO::load_command
LC_REQ_DYLD = 0x80000000u
};
enum LoadCommandType LLVM_ENUM_INT_TYPE(uint32_t) {
enum LoadCommandType : uint32_t {
// Constants for the "cmd" field in llvm::MachO::load_command
LC_SEGMENT = 0x00000001u,
LC_SYMTAB = 0x00000002u,
@ -131,7 +131,7 @@ namespace llvm {
LC_LINKER_OPTIONS = 0x0000002Du
};
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Constant bits for the "flags" field in llvm::MachO::segment_command
SG_HIGHVM = 0x1u,
SG_FVMLIB = 0x2u,
@ -174,7 +174,7 @@ namespace llvm {
S_THREAD_LOCAL_INIT_FUNCTION_POINTERS = 0x15u
};
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Constant masks for the "flags[31:24]" field in llvm::MachO::section and
// llvm::MachO::section_64 (mask "flags" with SECTION_ATTRIBUTES_USR)
S_ATTR_PURE_INSTRUCTIONS = 0x80000000u,
@ -348,7 +348,7 @@ namespace llvm {
N_LENG = 0xFEu
};
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Constant values for the r_symbolnum field in an
// llvm::MachO::relocation_info structure when r_extern is 0.
R_ABS = 0,
@ -893,7 +893,7 @@ namespace llvm {
}
// Enums from <mach/machine.h>
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Capability bits used in the definition of cpu_type.
CPU_ARCH_MASK = 0xff000000, // Mask for architecture bits
CPU_ARCH_ABI64 = 0x01000000 // 64 bit ABI
@ -913,7 +913,7 @@ namespace llvm {
CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
};
enum LLVM_ENUM_INT_TYPE(uint32_t) {
enum : uint32_t {
// Capability bits used in the definition of cpusubtype.
CPU_SUB_TYPE_MASK = 0xff000000, // Mask for architecture bits
CPU_SUB_TYPE_LIB64 = 0x80000000, // 64 bit libraries

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@ -144,7 +144,7 @@ namespace {
// not be erased.
bool isBulkSpilling;
enum LLVM_ENUM_INT_TYPE(unsigned) {
enum : unsigned {
spillClean = 1,
spillDirty = 100,
spillImpossible = ~0u

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@ -247,7 +247,7 @@ class RAGreedy : public MachineFunctionPass,
/// class.
SmallVector<GlobalSplitCandidate, 32> GlobalCand;
enum LLVM_ENUM_INT_TYPE(unsigned) { NoCand = ~0u };
enum : unsigned { NoCand = ~0u };
/// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
/// NoCand which indicates the stack interval.