RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-08 04:52:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600/SI: Refactor SOP1 classes

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229152 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-02-13 21:02:37 +00:00
parent ad4bb96a12
commit 193679b6ae
1 changed files with 19 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
lib/Target/R600/SIInstrInfo.td
View File

@ -392,27 +392,26 @@ class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
SOP1e <op.VI>,
SIMCInstr<opName, SISubtarget.VI>;
multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
pattern>;
multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
list<dag> pattern> {
def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
opName#" $dst, $src0">;
def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
opName#" $dst, $src0">;
}
multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
pattern>;
multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
opName#" $dst, $src0", pattern
>;
def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0">;
def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0">;
}
multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0", pattern
>;
// no input, 64-bit output.
multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
@ -430,16 +429,10 @@ multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
}
// 64-bit input, 32-bit output.
multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
pattern>;
def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0">;
def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0">;
}
multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0", pattern
>;
class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
SOP2<outs, ins, "", pattern>,