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[X86][SSE] Added vector mul combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
cbaa900ad9
commit
1982c8eed7
249
test/CodeGen/X86/combine-mul.ll
Normal file
249
test/CodeGen/X86/combine-mul.ll
Normal file
@ -0,0 +1,249 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (mul undef, x) -> 0
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define <4 x i32> @combine_vec_mul_undef0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = mul <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (mul x, undef) -> 0
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define <4 x i32> @combine_vec_mul_undef1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (mul x, 0) -> 0
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define <4 x i32> @combine_vec_mul_zero(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_zero:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_zero:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, zeroinitializer
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ret <4 x i32> %1
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}
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; fold (mul x, 0) -> 0
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define <4 x i32> @combine_vec_mul_one(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_one:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_one:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %1
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}
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; fold (mul x, -1) -> 0-x
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define <4 x i32> @combine_vec_mul_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negone:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negone:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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; fold (mul x, (1 << c)) -> x << c
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define <4 x i32> @combine_vec_mul_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 1, i32 2, i32 4, i32 16>
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ret <4 x i32> %1
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}
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; fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
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define <4 x i32> @combine_vec_mul_negpow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negpow2a:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negpow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -2, i32 -2, i32 -2, i32 -2>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_mul_negpow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_negpow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_negpow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = mul <4 x i32> %x, <i32 -1, i32 -2, i32 -4, i32 -16>
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ret <4 x i32> %1
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}
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; (mul (shl X, c1), c2) -> (mul X, c2 << c1)
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define <4 x i32> @combine_vec_mul_shl_const(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_shl_const:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_const:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, <i32 1, i32 3, i32 5, i32 7>
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ret <4 x i32> %2
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}
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; (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one use.
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define <4 x i32> @combine_vec_mul_shl_oneuse0(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_oneuse0:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld %xmm1, %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_oneuse0:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, %y
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_mul_shl_oneuse1(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_oneuse1:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld %xmm1, %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_oneuse1:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %y, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_mul_shl_multiuse0(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_multiuse0:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld %xmm0, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_multiuse0:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, %y
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @combine_vec_mul_shl_multiuse1(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_mul_shl_multiuse1:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld %xmm0, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_shl_multiuse1:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %y, %1
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%3 = add <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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; fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
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define <4 x i32> @combine_vec_mul_add(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_mul_add:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_mul_add:
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; AVX: # BB#0:
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; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = add <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
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%2 = mul <4 x i32> %1, <i32 4, i32 6, i32 2, i32 0>
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ret <4 x i32> %2
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}
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