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Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-12-29 03:34:54 +00:00
parent d62c16e535
commit 19ec2a9db1
1 changed files with 9 additions and 10 deletions
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19
lib/Target/X86/X86ISelLowering.cpp
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@ -5182,17 +5182,16 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
if (VT.getSizeInBits() == 256) {
EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2);
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item);
SDValue ZeroVec = getZeroVector(VT, true, DAG, dl);
return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
DAG, dl);
}
assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasXMMInt(), DAG);
if (VT.getSizeInBits() == 256) {
SDValue ZeroVec = getZeroVector(MVT::v8i32, true, DAG, dl);
Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
DAG, dl);
} else {
assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasXMMInt(), DAG);
}
return DAG.getNode(ISD::BITCAST, dl, VT, Item);
}
}