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when transforming a MULHS into a wider MUL, there is no need to SRA the

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result, the top bits are truncated off anyway, just use SRL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-15 05:51:39 +00:00
parent ba3c815570
commit 1a0fbe2cf4
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1940,7 +1940,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) {
N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1, N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
DAG.getConstant(SimpleSize, getShiftAmountTy())); DAG.getConstant(SimpleSize, getShiftAmountTy()));
return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
} }