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[PowerPC] fix potential verification errors on CFENCE8

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This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs.

Differential Revision: https://reviews.llvm.org/D34208



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hiroshi Inoue 2017-06-15 16:51:28 +00:00
parent b0fa17fec7
commit 1a33599c52
4 changed files with 13 additions and 13 deletions
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2
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1964,7 +1964,7 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
case PPC::CFENCE8: {
auto Val = MI.getOperand(0).getReg();
BuildMI(MBB, MI, DL, get(PPC::CMPW), PPC::CR7).addReg(Val).addReg(Val);
BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
.addImm(PPC::PRED_NE_MINUS)
.addReg(PPC::CR7)

2
test/CodeGen/PowerPC/atomic-2.ll
View File

@ -109,7 +109,7 @@ entry:
%tmp = load atomic i64, i64* %mem acquire, align 64
; CHECK-NOT: ldarx
; CHECK: ld [[VAL:r[0-9]+]]
; CHECK: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
; CHECK: cmpd [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
; CHECK: bne- [[CR]], .+4
; CHECK: isync
ret i64 %tmp

2
test/CodeGen/PowerPC/atomics-constant.ll
View File

@ -11,7 +11,7 @@ define i64 @foo() {
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: cmpw 7, 4, 4
; CHECK-NEXT: cmpd 7, 4, 4
; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync

20
test/CodeGen/PowerPC/atomics-regression.ll
View File

@ -23,7 +23,7 @@ define i8 @test2(i8* %ptr) {
; PPC64LE-LABEL: test2:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -37,7 +37,7 @@ define i8 @test3(i8* %ptr) {
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -67,7 +67,7 @@ define i16 @test6(i16* %ptr) {
; PPC64LE-LABEL: test6:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -81,7 +81,7 @@ define i16 @test7(i16* %ptr) {
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -111,7 +111,7 @@ define i32 @test10(i32* %ptr) {
; PPC64LE-LABEL: test10:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -125,7 +125,7 @@ define i32 @test11(i32* %ptr) {
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -155,7 +155,7 @@ define i64 @test14(i64* %ptr) {
; PPC64LE-LABEL: test14:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -169,7 +169,7 @@ define i64 @test15(i64* %ptr) {
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
@ -9566,7 +9566,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
; PPC64LE-LABEL: test_ordering0:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: lwz 4, 0(3)
; PPC64LE-NEXT: cmpw 7, 4, 4
; PPC64LE-NEXT: cmpd 7, 4, 4
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: lwz 3, 0(3)
@ -9583,7 +9583,7 @@ define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
; PPC64LE-LABEL: test_ordering1:
; PPC64LE: # BB#0:
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpw 7, 3, 3
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: stw 4, 0(5)