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[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -155,6 +155,9 @@ static void LowerLargeShift(MCInst& Inst) {
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case Mips::DSRA:
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Inst.setOpcode(Mips::DSRA32);
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return;
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case Mips::DROTR:
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Inst.setOpcode(Mips::DROTR32);
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return;
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}
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}
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@ -206,6 +209,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case Mips::DSLL:
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case Mips::DSRL:
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case Mips::DSRA:
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case Mips::DROTR:
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LowerLargeShift(TmpInst);
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break;
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// Double extract instruction is chosen by pos and size operands
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@ -111,6 +111,7 @@ let Predicates = [HasMips64r2, HasStdEnc] in {
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SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
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SRLV_FM<0x16, 1>;
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def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>;
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}
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/// Load and Store Instructions
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@ -1,4 +1,4 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
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# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
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# Check that the assembler can handle the documented syntax
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# for arithmetic and logical instructions.
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#------------------------------------------------------------------------------
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@ -73,6 +73,8 @@
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# CHECK: daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64]
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# CHECK: daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65]
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# CHECK: daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00]
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# CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
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# CHECK: drotr32 $9, $6, 52 # encoding: [0x3e,0x4d,0x26,0x00]
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# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
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# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
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# CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
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@ -94,6 +96,8 @@
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daddiu $9,$6,-15001
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daddiu $9,-15001
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daddu $9,$6,$7
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drotr $9, $6, 20
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drotr32 $9, $6, 52
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madd $6,$7
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maddu $6,$7
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msub $6,$7
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