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Make FP zero to be legal FP immediate via LOAD ZERO

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76034 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 14:24:16 +00:00
parent 5753f47f5b
commit 1ada84daaf
2 changed files with 48 additions and 0 deletions
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5
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -51,6 +51,11 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
if (!UseSoftFloat) {
addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
addLegalFPImmediate(APFloat(+0.0)); // lzer
addLegalFPImmediate(APFloat(+0.0f)); // lzdr
addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
}
// Compute derived properties from the register classes

43
lib/Target/SystemZ/SystemZInstrFP.td
View File

@ -14,6 +14,17 @@
// FIXME: multiclassify!
//===----------------------------------------------------------------------===//
// FP Pattern fragments
def fpimm0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(+0.0);
}]>;
def fpimmneg0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(-0.0);
}]>;
let usesCustomDAGSchedInserter = 1 in {
def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
"# SelectF32 PSEUDO",
@ -28,6 +39,16 @@ let usesCustomDAGSchedInserter = 1 in {
//===----------------------------------------------------------------------===//
// Move Instructions
// Floating point constant loads.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
"lzer\t{$dst}",
[(set FP32:$dst, fpimm0)]>;
def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
"lzdr\t{$dst}",
[(set FP64:$dst, fpimm0)]>;
}
let neverHasSideEffects = 1 in {
def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"ler\t{$dst, $src}",
@ -211,6 +232,20 @@ def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
} // isTwoAddress = 1
def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"sqebr\t{$dst, $src}",
[(set FP32:$dst, (fsqrt FP32:$src))]>;
def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"sqdbr\t{$dst, $src}",
[(set FP64:$dst, (fsqrt FP64:$src))]>;
def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
"sqeb\t{$dst, $src}",
[(set FP32:$dst, (fsqrt (load rriaddr:$src)))]>;
def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
"sqdb\t{$dst, $src}",
[(set FP64:$dst, (fsqrt (load rriaddr:$src)))]>;
def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
"ledbr\t{$dst, $src}",
[(set FP32:$dst, (fround FP64:$src))]>;
@ -281,3 +316,11 @@ def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
[(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
(implicit PSW)]>;
} // Defs = [PSW]
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
// Floating point constant -0.0
def : Pat<(f32 fpimmneg0), (FNEG32rr (LD_Fp032))>;
def : Pat<(f64 fpimmneg0), (FNEG64rr (LD_Fp064))>;