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[Hexagon] Merging nops in to previous packet rather than always creating a new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
42b983d1a7
commit
1baab3bf65
@ -11,7 +11,10 @@
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#include "HexagonFixupKinds.h"
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#include "HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCChecker.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCShuffler.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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@ -41,6 +44,19 @@ class HexagonAsmBackend : public MCAsmBackend {
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std::unique_ptr <MCInstrInfo> MCII;
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std::unique_ptr <MCInst *> RelaxTarget;
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MCInst * Extender;
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void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
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MCInst &HMB) const {
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SmallVector<MCFixup, 4> Fixups;
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SmallString<256> Code;
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raw_svector_ostream VecOS(Code);
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E.encodeInstruction(HMB, VecOS, Fixups, RF.getSubtargetInfo());
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// Update the fragment.
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RF.setInst(HMB);
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RF.getContents() = Code;
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RF.getFixups() = Fixups;
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}
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public:
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HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :
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OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
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@ -530,23 +546,7 @@ public:
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///
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/// \param Inst - The instruction to test.
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bool mayNeedRelaxation(MCInst const &Inst) const override {
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assert(HexagonMCInstrInfo::isBundle(Inst));
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bool PreviousIsExtender = false;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
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auto const &Inst = *I.getInst();
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if (!PreviousIsExtender) {
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if (HexagonMCInstrInfo::isDuplex(*MCII, Inst)) {
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if (isInstRelaxable(*Inst.getOperand(0).getInst()) ||
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isInstRelaxable(*Inst.getOperand(1).getInst()))
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return true;
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} else {
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if (isInstRelaxable(Inst))
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return true;
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}
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}
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PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
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}
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return false;
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return true;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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@ -686,6 +686,58 @@ public:
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}
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return true;
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}
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void finishLayout(MCAssembler const &Asm,
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MCAsmLayout &Layout) const override {
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for (auto I : Layout.getSectionOrder()) {
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auto &Fragments = I->getFragmentList();
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for (auto &J : Fragments) {
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switch (J.getKind()) {
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default:
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break;
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case MCFragment::FT_Align: {
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auto Size = Asm.computeFragmentSize(Layout, J);
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for (auto K = J.getIterator();
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K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
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--K;
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switch (K->getKind()) {
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default:
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break;
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case MCFragment::FT_Align: {
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// Don't pad before other alignments
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Size = 0;
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break;
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}
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case MCFragment::FT_Relaxable: {
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auto &RF = cast<MCRelaxableFragment>(*K);
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auto &Inst = const_cast<MCInst &>(RF.getInst());
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while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) {
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MCInst *Nop = new (Asm.getContext()) MCInst;
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Nop->setOpcode(Hexagon::A2_nop);
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Inst.addOperand(MCOperand::createInst(Nop));
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Size -= 4;
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if (!HexagonMCChecker(
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*MCII, RF.getSubtargetInfo(), Inst, Inst,
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*Asm.getContext().getRegisterInfo()).check()) {
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Inst.erase(Inst.end() - 1);
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Size = 0;
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}
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}
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bool Error = HexagonMCShuffle(*MCII, RF.getSubtargetInfo(), Inst);
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//assert(!Error);
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(void)Error;
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ReplaceInstruction(Asm.getEmitter(), RF, Inst);
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Layout.invalidateFragmentsFrom(&RF);
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Size = 0; // Only look back one instruction
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break;
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}
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}
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}
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}
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}
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}
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}
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}
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};
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} // end anonymous namespace
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60
test/MC/Hexagon/align.s
Normal file
60
test/MC/Hexagon/align.s
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@ -0,0 +1,60 @@
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# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
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# Verify that the .align directive emits the proper insn packets.
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{ r1 = sub(#1, r1) }
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# CHECK: 76414021 { r1 = sub(#1, r1)
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# CHECK-NEXT: 7f004000 nop
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# CHECK-NEXT: 7f004000 nop
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# CHECK-NEXT: 7f00c000 nop }
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.align 16
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{ r1 = sub(#1, r1)
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r2 = sub(#1, r2) }
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# CHECK: 76414021 { r1 = sub(#1, r1)
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# CHECK-NEXT: 76424022 r2 = sub(#1, r2)
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# CHECK-NEXT: 7f004000 nop
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# CHECK-NEXT: 7f00c000 nop }
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.p2align 5
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{ r1 = sub(#1, r1)
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r2 = sub(#1, r2)
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r3 = sub(#1, r3) }
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# CHECK: 76434023 r3 = sub(#1, r3)
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# CHECK-NEXT: 7f00c000 nop }
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.align 16
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{ r1 = sub(#1, r1)
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r2 = sub(#1, r2)
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r3 = sub(#1, r3)
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r4 = sub(#1, r4) }
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# Don't pad packets that can't be padded e.g. solo insts
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# CHECK: 9200c020 { r0 = vextract(v0,r0) }
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r0 = vextract(v0, r0)
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.align 128
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# CHECK: 76414021 { r1 = sub(#1, r1)
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# CHECK-NEXT: 7f00c000 nop }
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{ r1 = sub(#1, r1) }
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#CHECK: { r1 = sub(#1, r1)
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#CHECK: r2 = sub(#1, r2)
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#CHECK: r3 = sub(#1, r3) }
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.falign
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.align 8
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{ r1 = sub(#1, r1)
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r2 = sub(#1, r2)
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r3 = sub(#1, r3) }
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# CHECK: { immext(#0)
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# CHECK: r0 = sub(##1, r0)
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# CHECK: immext(#0)
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# CHECK: r1 = sub(##1, r1) }
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# CHECK: { nop
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# CHECK: nop
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# CHECK: nop }
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# CHECK: { r0 = sub(#1, r0) }
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{ r0 = sub (##1, r0)
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r1 = sub (##1, r1) }
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.align 16
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{ r0 = sub (#1, r0) }
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