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[PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
816c06f7fa
commit
1bc147c091
@ -422,7 +422,8 @@ void PPCOperand::print(raw_ostream &OS) const {
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void PPCAsmParser::
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ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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int Opcode = Inst.getOpcode();
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switch (Opcode) {
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case PPC::LAx: {
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MCInst TmpInst;
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TmpInst.setOpcode(PPC::LA);
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@ -472,10 +473,82 @@ ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case PPC::SLWI: {
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case PPC::EXTLWI:
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case PPC::EXTLWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLWINM);
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(B));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(N - 1));
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Inst = TmpInst;
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break;
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}
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case PPC::EXTRWI:
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case PPC::EXTRWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(B + N));
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TmpInst.addOperand(MCOperand::CreateImm(32 - N));
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TmpInst.addOperand(MCOperand::CreateImm(31));
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Inst = TmpInst;
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break;
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}
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case PPC::INSLWI:
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case PPC::INSLWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(32 - B));
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TmpInst.addOperand(MCOperand::CreateImm(B));
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TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
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Inst = TmpInst;
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break;
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}
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case PPC::INSRWI:
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case PPC::INSRWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
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TmpInst.addOperand(MCOperand::CreateImm(B));
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TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
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Inst = TmpInst;
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break;
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}
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case PPC::ROTRWI:
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case PPC::ROTRWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(32 - N));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(31));
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Inst = TmpInst;
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break;
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}
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case PPC::SLWI:
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case PPC::SLWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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@ -484,10 +557,11 @@ ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case PPC::SRWI: {
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case PPC::SRWI:
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case PPC::SRWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLWINM);
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TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(32 - N));
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@ -496,10 +570,90 @@ ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case PPC::SLDI: {
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case PPC::CLRRWI:
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case PPC::CLRRWIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLDICR);
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TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(31 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::CLRLSLWI:
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case PPC::CLRLSLWIo: {
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MCInst TmpInst;
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int64_t B = Inst.getOperand(2).getImm();
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int64_t N = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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TmpInst.addOperand(MCOperand::CreateImm(B - N));
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TmpInst.addOperand(MCOperand::CreateImm(31 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::EXTLDI:
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case PPC::EXTLDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(B));
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TmpInst.addOperand(MCOperand::CreateImm(N - 1));
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Inst = TmpInst;
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break;
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}
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case PPC::EXTRDI:
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case PPC::EXTRDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(B + N));
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TmpInst.addOperand(MCOperand::CreateImm(64 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::INSRDI:
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case PPC::INSRDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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int64_t B = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
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TmpInst.addOperand(MCOperand::CreateImm(B));
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Inst = TmpInst;
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break;
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}
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case PPC::ROTRDI:
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case PPC::ROTRDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(64 - N));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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Inst = TmpInst;
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break;
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}
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case PPC::SLDI:
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case PPC::SLDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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@ -507,10 +661,11 @@ ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case PPC::SRDI: {
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case PPC::SRDI:
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case PPC::SRDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLDICL);
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TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(64 - N));
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@ -518,6 +673,31 @@ ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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case PPC::CLRRDI:
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case PPC::CLRRDIo: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(63 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::CLRLSLDI:
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case PPC::CLRLSLDIo: {
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MCInst TmpInst;
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int64_t B = Inst.getOperand(2).getImm();
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int64_t N = Inst.getOperand(3).getImm();
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TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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TmpInst.addOperand(MCOperand::CreateImm(B - N));
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Inst = TmpInst;
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break;
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}
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}
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}
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@ -2290,14 +2290,89 @@ def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
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def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
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def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
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def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
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(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
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def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
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def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
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def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
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def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
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def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
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def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
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def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
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def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
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def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
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def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
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def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
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def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
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def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
||||
def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
||||
def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
||||
def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
||||
def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
|
||||
def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
|
||||
def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
|
||||
(ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
|
||||
|
||||
def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
|
||||
def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
|
||||
def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
|
||||
def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
|
||||
def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
|
||||
def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
|
||||
|
||||
// These generic branch instruction forms are used for the assembler parser only.
|
||||
// Defs and Uses are conservative, since we don't know the BO value.
|
||||
|
||||
@ -1848,57 +1848,99 @@
|
||||
|
||||
# Rotate and shift mnemonics
|
||||
|
||||
# FIXME: extldi 2, 3, 4, 5
|
||||
# FIXME: extldi. 2, 3, 4, 5
|
||||
# FIXME: extrdi 2, 3, 4, 5
|
||||
# FIXME: extrdi. 2, 3, 4, 5
|
||||
# FIXME: insrdi 2, 3, 4, 5
|
||||
# FIXME: insrdi. 2, 3, 4, 5
|
||||
# FIXME: rotldi 2, 3, 4
|
||||
# FIXME: rotldi. 2, 3, 4
|
||||
# FIXME: rotrdi 2, 3, 4
|
||||
# FIXME: rotrdi. 2, 3, 4
|
||||
# FIXME: rotld 2, 3, 4
|
||||
# FIXME: rotld. 2, 3, 4
|
||||
# CHECK: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4]
|
||||
extldi 2, 3, 4, 5
|
||||
# CHECK: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5]
|
||||
extldi. 2, 3, 4, 5
|
||||
# CHECK: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20]
|
||||
extrdi 2, 3, 4, 5
|
||||
# CHECK: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21]
|
||||
extrdi. 2, 3, 4, 5
|
||||
# CHECK: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e]
|
||||
insrdi 2, 3, 4, 5
|
||||
# CHECK: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f]
|
||||
insrdi. 2, 3, 4, 5
|
||||
# CHECK: rldicl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x00]
|
||||
rotldi 2, 3, 4
|
||||
# CHECK: rldicl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x01]
|
||||
rotldi. 2, 3, 4
|
||||
# CHECK: rldicl 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x02]
|
||||
rotrdi 2, 3, 4
|
||||
# CHECK: rldicl. 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x03]
|
||||
rotrdi. 2, 3, 4
|
||||
# CHECK: rldcl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x10]
|
||||
rotld 2, 3, 4
|
||||
# CHECK: rldcl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x11]
|
||||
rotld. 2, 3, 4
|
||||
# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4]
|
||||
sldi 2, 3, 4
|
||||
# FIXME: sldi. 2, 3, 4
|
||||
# CHECK: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5]
|
||||
sldi. 2, 3, 4
|
||||
# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02]
|
||||
srdi 2, 3, 4
|
||||
# FIXME: srdi. 2, 3, 4
|
||||
# FIXME: clrldi 2, 3, 4
|
||||
# FIXME: clrldi. 2, 3, 4
|
||||
# FIXME: clrrdi 2, 3, 4
|
||||
# FIXME: clrrdi. 2, 3, 4
|
||||
# FIXME: clrlsldi 2, 3, 4, 5
|
||||
# FIXME: clrlsldi. 2, 3, 4, 5
|
||||
# CHECK: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03]
|
||||
srdi. 2, 3, 4
|
||||
# CHECK: rldicl 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x00]
|
||||
clrldi 2, 3, 4
|
||||
# CHECK: rldicl. 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x01]
|
||||
clrldi. 2, 3, 4
|
||||
# CHECK: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4]
|
||||
clrrdi 2, 3, 4
|
||||
# CHECK: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5]
|
||||
clrrdi. 2, 3, 4
|
||||
# CHECK: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48]
|
||||
clrlsldi 2, 3, 5, 4
|
||||
# CHECK: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49]
|
||||
clrlsldi. 2, 3, 5, 4
|
||||
|
||||
# FIXME: extlwi 2, 3, 4, 5
|
||||
# FIXME: extlwi. 2, 3, 4, 5
|
||||
# FIXME: extrwi 2, 3, 4, 5
|
||||
# FIXME: extrwi. 2, 3, 4, 5
|
||||
# FIXME: inslwi 2, 3, 4, 5
|
||||
# FIXME: inslwi. 2, 3, 4, 5
|
||||
# FIXME: insrwi 2, 3, 4, 5
|
||||
# FIXME: insrwi. 2, 3, 4, 5
|
||||
# FIXME: rotlwi 2, 3, 4
|
||||
# FIXME: rotlwi. 2, 3, 4
|
||||
# FIXME: rotrwi 2, 3, 4
|
||||
# FIXME: rotrwi. 2, 3, 4
|
||||
# FIXME: rotlw 2, 3, 4
|
||||
# FIXME: rotlw. 2, 3, 4
|
||||
# CHECK: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06]
|
||||
extlwi 2, 3, 4, 5
|
||||
# CHECK: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07]
|
||||
extlwi. 2, 3, 4, 5
|
||||
# CHECK: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e]
|
||||
extrwi 2, 3, 4, 5
|
||||
# CHECK: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f]
|
||||
extrwi. 2, 3, 4, 5
|
||||
# CHECK: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50]
|
||||
inslwi 2, 3, 4, 5
|
||||
# CHECK: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51]
|
||||
inslwi. 2, 3, 4, 5
|
||||
# CHECK: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50]
|
||||
insrwi 2, 3, 4, 5
|
||||
# CHECK: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51]
|
||||
insrwi. 2, 3, 4, 5
|
||||
# CHECK: rlwinm 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3e]
|
||||
rotlwi 2, 3, 4
|
||||
# CHECK: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3f]
|
||||
rotlwi. 2, 3, 4
|
||||
# CHECK: rlwinm 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3e]
|
||||
rotrwi 2, 3, 4
|
||||
# CHECK: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3f]
|
||||
rotrwi. 2, 3, 4
|
||||
# CHECK: rlwnm 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3e]
|
||||
rotlw 2, 3, 4
|
||||
# CHECK: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3f]
|
||||
rotlw. 2, 3, 4
|
||||
# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36]
|
||||
slwi 2, 3, 4
|
||||
# FIXME: slwi. 2, 3, 4
|
||||
# CHECK: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37]
|
||||
slwi. 2, 3, 4
|
||||
# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e]
|
||||
srwi 2, 3, 4
|
||||
# FIXME: srwi. 2, 3, 4
|
||||
# FIXME: clrlwi 2, 3, 4
|
||||
# FIXME: clrlwi. 2, 3, 4
|
||||
# FIXME: clrrwi 2, 3, 4
|
||||
# FIXME: clrrwi. 2, 3, 4
|
||||
# FIXME: clrlslwi 2, 3, 4, 5
|
||||
# FIXME: clrlslwi. 2, 3, 4, 5
|
||||
# CHECK: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f]
|
||||
srwi. 2, 3, 4
|
||||
# CHECK: rlwinm 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3e]
|
||||
clrlwi 2, 3, 4
|
||||
# CHECK: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3f]
|
||||
clrlwi. 2, 3, 4
|
||||
# CHECK: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36]
|
||||
clrrwi 2, 3, 4
|
||||
# CHECK: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37]
|
||||
clrrwi. 2, 3, 4
|
||||
# CHECK: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76]
|
||||
clrlslwi 2, 3, 5, 4
|
||||
# CHECK: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77]
|
||||
clrlslwi. 2, 3, 5, 4
|
||||
|
||||
# Move to/from special purpose register mnemonics
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user