mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-12 22:26:14 +00:00
R600/SI: Fix hardcoded values for modifiers.
Move enums to SIDefines.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
49cbc1891b
commit
1bcadc9b5c
@ -9,6 +9,8 @@
|
|||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#include "AMDGPUInstPrinter.h"
|
#include "AMDGPUInstPrinter.h"
|
||||||
|
#include "SIDefines.h"
|
||||||
|
|
||||||
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
|
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
|
||||||
#include "llvm/MC/MCExpr.h"
|
#include "llvm/MC/MCExpr.h"
|
||||||
#include "llvm/MC/MCInst.h"
|
#include "llvm/MC/MCInst.h"
|
||||||
@ -239,12 +241,12 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
|||||||
void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
|
void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
|
||||||
raw_ostream &O) {
|
raw_ostream &O) {
|
||||||
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
|
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
|
||||||
if (InputModifiers & 0x1)
|
if (InputModifiers & SISrcMods::NEG)
|
||||||
O << '-';
|
O << '-';
|
||||||
if (InputModifiers & 0x2)
|
if (InputModifiers & SISrcMods::ABS)
|
||||||
O << '|';
|
O << '|';
|
||||||
printOperand(MI, OpNo + 1, O);
|
printOperand(MI, OpNo + 1, O);
|
||||||
if (InputModifiers & 0x2)
|
if (InputModifiers & SISrcMods::ABS)
|
||||||
O << '|';
|
O << '|';
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -27,6 +27,22 @@ enum {
|
|||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
namespace SIInstrFlags {
|
||||||
|
enum Flags {
|
||||||
|
// First 4 bits are the instruction encoding
|
||||||
|
VM_CNT = 1 << 0,
|
||||||
|
EXP_CNT = 1 << 1,
|
||||||
|
LGKM_CNT = 1 << 2
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
namespace SISrcMods {
|
||||||
|
enum {
|
||||||
|
NEG = 1 << 0,
|
||||||
|
ABS = 1 << 1
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
|
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
|
||||||
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
|
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
|
||||||
#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
|
#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
|
||||||
|
@ -19,6 +19,7 @@
|
|||||||
#include "AMDGPU.h"
|
#include "AMDGPU.h"
|
||||||
#include "AMDGPUSubtarget.h"
|
#include "AMDGPUSubtarget.h"
|
||||||
#include "SIInstrInfo.h"
|
#include "SIInstrInfo.h"
|
||||||
|
#include "SIDefines.h"
|
||||||
#include "SIMachineFunctionInfo.h"
|
#include "SIMachineFunctionInfo.h"
|
||||||
#include "llvm/CodeGen/MachineFunction.h"
|
#include "llvm/CodeGen/MachineFunction.h"
|
||||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||||
|
@ -270,20 +270,4 @@ enum Offsets {
|
|||||||
|
|
||||||
} // End namespace llvm
|
} // End namespace llvm
|
||||||
|
|
||||||
namespace SIInstrFlags {
|
|
||||||
enum Flags {
|
|
||||||
// First 4 bits are the instruction encoding
|
|
||||||
VM_CNT = 1 << 0,
|
|
||||||
EXP_CNT = 1 << 1,
|
|
||||||
LGKM_CNT = 1 << 2
|
|
||||||
};
|
|
||||||
}
|
|
||||||
|
|
||||||
namespace SISrcMods {
|
|
||||||
enum {
|
|
||||||
NEG = 1 << 0,
|
|
||||||
ABS = 1 << 1
|
|
||||||
};
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
Loading…
Reference in New Issue
Block a user