[mips] Add instruction selection patterns for blez and bgez.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-05-21 17:13:47 +00:00
parent b9c26dcb24
commit 1d4d32398d
4 changed files with 47 additions and 1 deletions

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@ -294,6 +294,11 @@ def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
(BLEZ64 i64:$lhs, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
(BGEZ64 i64:$lhs, bb:$dst)>;
// setcc patterns
defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
defm : SetlePats<CPU64Regs, SLT64, SLTu64>;

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@ -1277,6 +1277,11 @@ def : MipsPat<(brcond RC:$cond, bb:$dst),
defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
(BLEZ i32:$lhs, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
(BGEZ i32:$lhs, bb:$dst)>;
// setcc patterns
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
Instruction SLTuOp, Register ZEROReg> {

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@ -0,0 +1,36 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
; CHECK: test_blez:
; CHECK: blez ${{[0-9]+}}, $BB
define void @test_blez(i32 %a) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end
if.then:
tail call void @foo1()
br label %if.end
if.end:
ret void
}
declare void @foo1()
; CHECK: test_bgez:
; CHECK: bgez ${{[0-9]+}}, $BB
define void @test_bgez(i32 %a) {
entry:
%cmp = icmp slt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end
if.then:
tail call void @foo1()
br label %if.end
if.end:
ret void
}

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@ -131,7 +131,7 @@ declare void @foo11()
; filled.
;
; SUCCBB: succbbs_loop1:
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
; SUCCBB: blez $5, $BB
; SUCCBB-NEXT: addiu
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
; SUCCBB-NEXT: addiu