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Teach BasicAA about arm.neon.vld1 and vst1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2011-04-27 20:44:28 +00:00
parent 0be77dff11
commit 1d7e818a38
2 changed files with 36 additions and 0 deletions
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20
lib/Analysis/BasicAliasAnalysis.cpp
View File

@ -779,6 +779,26 @@ BasicAliasAnalysis::getModRefInfo(ImmutableCallSite CS,
return NoModRef;
break;
}
case Intrinsic::arm_neon_vld1: {
// LLVM's vld1 and vst1 intrinsics currently only support a single
// vector register.
uint64_t Size =
TD ? TD->getTypeStoreSize(II->getType()) : UnknownSize;
if (isNoAlias(Location(II->getArgOperand(0), Size,
II->getMetadata(LLVMContext::MD_tbaa)),
Loc))
return NoModRef;
break;
}
case Intrinsic::arm_neon_vst1: {
uint64_t Size =
TD ? TD->getTypeStoreSize(II->getArgOperand(1)->getType()) : UnknownSize;
if (isNoAlias(Location(II->getArgOperand(0), Size,
II->getMetadata(LLVMContext::MD_tbaa)),
Loc))
return NoModRef;
break;
}
}
// The AliasAnalysis base class has some smarts, lets use them.

16
test/Analysis/BasicAA/intrinsics.ll
View File

@ -19,5 +19,21 @@ entry:
ret <8 x i16> %c
}
; CHECK: define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %q = getelementptr i8* %p, i64 16
; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
; CHECK-NEXT: %c = add <8 x i16> %a, %a
define <8 x i16> @test1(i8* %p, <8 x i16> %y) {
entry:
%q = getelementptr i8* %p, i64 16
%a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16)
%b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind
%c = add <8 x i16> %a, %b
ret <8 x i16> %c
}
declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly
declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind