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Check Reg against zero.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102573 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-04-29 00:59:34 +00:00
parent 6691a8935c
commit 1deef27b0a
2 changed files with 3 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -3699,7 +3699,7 @@ SelectionDAGBuilder::EmitFuncArgumentDbgValue(const DbgValueInst &DI,
unsigned Reg = 0;
if (N.getOpcode() == ISD::CopyFromReg) {
Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned PR = RegInfo.getLiveInPhysReg(Reg);
if (PR)

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -222,6 +222,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
unsigned Reg = MI->getOperand(0).getReg();
if (!Reg)
continue;
if (TargetRegisterInfo::isPhysicalRegister(Reg))
EntryMBB->insert(EntryMBB->begin(), MI);
else {