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Add AVX SSE2 packed integer extract/insert instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-06-30 17:03:03 +00:00
parent 2e502577ab
commit 1e4b723b20
3 changed files with 66 additions and 17 deletions
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59
lib/Target/X86/X86InstrSSE.td
View File

@ -2805,32 +2805,57 @@ let Constraints = "$src1 = $dst" in {
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
// SSE2 - Packed Misc Integer Instructions
// SSE2 - Packed Integer Extract and Insert
//===---------------------------------------------------------------------===//
let ExeDomain = SSEPackedInt in {
multiclass sse2_pinsrw<bit Is2Addr = 1> {
def rri : Ii8<0xC4, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1,
GR32:$src2, i32i8imm:$src3),
!if(Is2Addr,
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst,
(X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
def rmi : Ii8<0xC4, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1,
i16mem:$src2, i32i8imm:$src3),
!if(Is2Addr,
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst,
(X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
imm:$src3))]>;
}
// Extract / Insert
// Extract
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
"vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
imm:$src2))]>, OpSize, VEX;
def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
imm:$src2))]>;
let Constraints = "$src1 = $dst" in {
def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1,
GR32:$src2, i32i8imm:$src3),
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1,
i16mem:$src2, i32i8imm:$src3),
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
imm:$src3))]>;
}
// Insert
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
let Constraints = "$src1 = $dst" in
defm VPINSRW : sse2_pinsrw, TB, OpSize;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
// SSE2 - Packed Misc Integer Instructions
//===---------------------------------------------------------------------===//
let ExeDomain = SSEPackedInt in {
// Mask creation
def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),

12
test/MC/AsmParser/X86/x86_32-encoding.s
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@ -11482,3 +11482,15 @@
// CHECK: encoding: [0xc5,0xe9,0x6d,0x18]
vpunpckhqdq (%eax), %xmm2, %xmm3
// CHECK: vpinsrw $7, %eax, %xmm2, %xmm3
// CHECK: encoding: [0xc5,0xe9,0xc4,0xd8,0x07]
vpinsrw $7, %eax, %xmm2, %xmm3
// CHECK: vpinsrw $7, (%eax), %xmm2, %xmm3
// CHECK: encoding: [0xc5,0xe9,0xc4,0x18,0x07]
vpinsrw $7, (%eax), %xmm2, %xmm3
// CHECK: vpextrw $7, %xmm2, %eax
// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
vpextrw $7, %xmm2, %eax

12
test/MC/AsmParser/X86/x86_64-encoding.s
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@ -1522,3 +1522,15 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0xc5,0x19,0x6d,0x28]
vpunpckhqdq (%rax), %xmm12, %xmm13
// CHECK: vpinsrw $7, %eax, %xmm12, %xmm13
// CHECK: encoding: [0xc5,0x19,0xc4,0xe8,0x07]
vpinsrw $7, %eax, %xmm12, %xmm13
// CHECK: vpinsrw $7, (%rax), %xmm12, %xmm13
// CHECK: encoding: [0xc5,0x19,0xc4,0x28,0x07]
vpinsrw $7, (%rax), %xmm12, %xmm13
// CHECK: vpextrw $7, %xmm12, %eax
// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
vpextrw $7, %xmm12, %eax