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Support insertps via the intrinsic and add a couple of simple

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testcases to make sure it's being generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2009-07-23 02:22:41 +00:00
parent 0f009d2ea5
commit 1e5cdea9d7
2 changed files with 27 additions and 2 deletions
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16
lib/Target/X86/X86InstrSSE.td
View File

@ -3590,15 +3590,19 @@ let Constraints = "$src1 = $dst" in {
defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
// insertps has a few different modes, there's the first two here below which
// are optimized inserts that won't zero arbitrary elements in the destination
// vector. The next one matches the intrinsic and could zero arbitrary elements
// in the target vector.
let Constraints = "$src1 = $dst" in {
multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
def match_rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst,
(X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
def match_rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@ -3608,6 +3612,14 @@ let Constraints = "$src1 = $dst" in {
}
}
let Constraints = "$src1 = $dst" in {
def INSERTPSrr : SS4AIi8<0x21, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
"insertps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst, (int_x86_sse41_insertps VR128:$src1,
VR128:$src2, imm:$src3))]>;
}
defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
let Defs = [EFLAGS] in {

13
test/CodeGen/X86/vec_insertps-1.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep insertps | count 2
define <4 x float> @t1(<4 x float> %t1, <4 x float> %t2) nounwind {
%tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
ret <4 x float> %tmp1
}
declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
define <4 x float> @t2(<4 x float> %t1, float %t2) nounwind {
%tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
ret <4 x float> %tmp1
}