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Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
5a11e02fbd
commit
1ed1e3ecd4
@ -46,9 +46,10 @@ namespace {
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SDValue IndexReg;
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int64_t Disp;
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bool isRI;
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SystemZRRIAddressMode()
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: BaseType(RegBase), IndexReg(), Disp(0) {
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SystemZRRIAddressMode(bool RI = false)
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: BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
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}
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void dump() {
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@ -61,9 +62,11 @@ namespace {
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} else {
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cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
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}
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if (!isRI) {
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cerr << "IndexReg ";
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if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
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else cerr << "nul";
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}
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cerr << " Disp " << Disp << '\n';
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}
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};
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@ -77,6 +80,8 @@ namespace {
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SystemZTargetLowering &Lowering;
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const SystemZSubtarget &Subtarget;
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void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp);
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void getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index);
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@ -109,9 +114,9 @@ namespace {
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#include "SystemZGenDAGISel.inc"
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private:
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bool SelectAddrRI32(const SDValue& Op, SDValue& Addr,
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bool SelectAddrRI12(SDValue Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp);
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bool SelectAddrRI(const SDValue& Op, SDValue& Addr,
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bool SelectAddrRI(SDValue Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp);
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bool SelectAddrRRI12(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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@ -124,6 +129,8 @@ namespace {
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bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit, unsigned Depth = 0);
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bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
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bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit);
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#ifndef NDEBUG
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unsigned Indent;
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@ -151,17 +158,6 @@ static bool isImmSExt20(int64_t Val, int64_t &Imm) {
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return false;
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}
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static bool isImmSExt20(SDNode *N, int64_t &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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return isImmSExt20(cast<ConstantSDNode>(N)->getSExtValue(), Imm);
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}
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static bool isImmSExt20(SDValue Op, int64_t &Imm) {
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return isImmSExt20(Op.getNode(), Imm);
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}
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/// isImmZExt12 - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// zero extension from a 12-bit value. If so, this returns true and the
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@ -174,139 +170,6 @@ static bool isImmZExt12(int64_t Val, int64_t &Imm) {
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return false;
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}
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static bool isImmZExt12(SDNode *N, int64_t &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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return isImmZExt12(cast<ConstantSDNode>(N)->getSExtValue(), Imm);
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}
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static bool isImmZExt12(SDValue Op, int64_t &Imm) {
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return isImmZExt12(Op.getNode(), Imm);
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}
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/// Returns true if the address can be represented by a base register plus
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/// an unsigned 12-bit displacement [r+imm].
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bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp) {
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// FIXME dl should come from parent load or store, not from address
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DebugLoc dl = Addr.getDebugLoc();
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MVT VT = Addr.getValueType();
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if (Addr.getOpcode() == ISD::ADD) {
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int64_t Imm = 0;
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if (isImmZExt12(Addr.getOperand(1), Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
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} else {
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Base = Addr.getOperand(0);
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}
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return true; // [r+i]
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}
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} else if (Addr.getOpcode() == ISD::OR) {
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int64_t Imm = 0;
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if (isImmZExt12(Addr.getOperand(1), Imm)) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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// provably disjoint.
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APInt LHSKnownZero, LHSKnownOne;
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CurDAG->ComputeMaskedBits(Addr.getOperand(0),
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APInt::getAllOnesValue(Addr.getOperand(0)
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.getValueSizeInBits()),
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LHSKnownZero, LHSKnownOne);
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if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
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// If all of the bits are known zero on the LHS or RHS, the add won't
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// carry.
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Base = Addr.getOperand(0);
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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return true;
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}
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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// Loading from a constant address.
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// If this address fits entirely in a 12-bit zext immediate field, codegen
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// this as "d(r0)"
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int64_t Imm;
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if (isImmZExt12(CN, Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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Base = CurDAG->getRegister(0, VT);
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return true;
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}
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}
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Disp = CurDAG->getTargetConstant(0, MVT::i64);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
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else
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Base = Addr;
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return true; // [r+0]
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}
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/// Returns true if the address can be represented by a base register plus
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/// a signed 20-bit displacement [r+imm].
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bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp) {
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// FIXME dl should come from parent load or store, not from address
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DebugLoc dl = Addr.getDebugLoc();
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MVT VT = Addr.getValueType();
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if (Addr.getOpcode() == ISD::ADD) {
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int64_t Imm = 0;
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if (isImmSExt20(Addr.getOperand(1), Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
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} else {
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Base = Addr.getOperand(0);
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}
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return true; // [r+i]
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}
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} else if (Addr.getOpcode() == ISD::OR) {
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int64_t Imm = 0;
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if (isImmSExt20(Addr.getOperand(1), Imm)) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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// provably disjoint.
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APInt LHSKnownZero, LHSKnownOne;
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CurDAG->ComputeMaskedBits(Addr.getOperand(0),
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APInt::getAllOnesValue(Addr.getOperand(0)
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.getValueSizeInBits()),
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LHSKnownZero, LHSKnownOne);
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if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
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// If all of the bits are known zero on the LHS or RHS, the add won't
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// carry.
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Base = Addr.getOperand(0);
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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return true;
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}
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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// Loading from a constant address.
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// If this address fits entirely in a 20-bit sext immediate field, codegen
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// this as "d(r0)"
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int64_t Imm;
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if (isImmSExt20(CN, Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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Base = CurDAG->getRegister(0, VT);
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return true;
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}
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}
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Disp = CurDAG->getTargetConstant(0, MVT::i64);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
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else
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Base = Addr;
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return true; // [r+0]
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}
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode.
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@ -360,7 +223,7 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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break;
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}
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// Test if the index field is free for use.
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if (AM.IndexReg.getNode()) {
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if (AM.IndexReg.getNode() && !AM.isRI) {
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AM = Backup;
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break;
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}
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@ -407,7 +270,8 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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// If we couldn't fold both operands into the address at the same time,
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// see if we can just put each operand into a register and fold at least
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// the add.
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if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
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if (!AM.isRI &&
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AM.BaseType == SystemZRRIAddressMode::RegBase &&
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!AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
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AM.Base.Reg = N.getNode()->getOperand(0);
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AM.IndexReg = N.getNode()->getOperand(1);
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@ -448,8 +312,8 @@ bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
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SystemZRRIAddressMode &AM) {
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// Is the base register already occupied?
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if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.getNode() == 0) {
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// If so, check to see if the scale register is set.
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if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
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AM.IndexReg = N;
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return false;
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}
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@ -464,22 +328,118 @@ bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
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return false;
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}
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void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index) {
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void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp) {
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if (AM.BaseType == SystemZRRIAddressMode::RegBase)
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Base = AM.Base.Reg;
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else
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Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
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Index = AM.IndexReg;
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
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}
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void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index) {
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getAddressOperandsRI(AM, Base, Disp);
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Index = AM.IndexReg;
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}
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/// Returns true if the address can be represented by a base register plus
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/// an unsigned 12-bit displacement [r+imm].
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bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp) {
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SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
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bool Done = false;
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if (!Addr.hasOneUse()) {
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unsigned Opcode = Addr.getOpcode();
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if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
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// If we are able to fold N into addressing mode, then we'll allow it even
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// if N has multiple uses. In general, addressing computation is used as
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// addresses by all of its uses. But watch out for CopyToReg uses, that
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// means the address computation is liveout. It will be computed by a LA
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// so we want to avoid computing the address twice.
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for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
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UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
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if (UI->getOpcode() == ISD::CopyToReg) {
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MatchAddressBase(Addr, AM12);
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Done = true;
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break;
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}
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}
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}
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}
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if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
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return false;
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// Check, whether we can match stuff using 20-bit displacements
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if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
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if (AM12.Disp == 0 && AM20.Disp != 0)
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return false;
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DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
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MVT VT = Addr.getValueType();
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if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
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if (!AM12.Base.Reg.getNode())
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AM12.Base.Reg = CurDAG->getRegister(0, VT);
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}
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assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
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getAddressOperandsRI(AM12, Base, Disp);
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return true;
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}
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/// Returns true if the address can be represented by a base register plus
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/// a signed 20-bit displacement [r+imm].
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bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp) {
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SystemZRRIAddressMode AM(/*isRI*/true);
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bool Done = false;
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if (!Addr.hasOneUse()) {
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unsigned Opcode = Addr.getOpcode();
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if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
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// If we are able to fold N into addressing mode, then we'll allow it even
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// if N has multiple uses. In general, addressing computation is used as
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// addresses by all of its uses. But watch out for CopyToReg uses, that
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// means the address computation is liveout. It will be computed by a LA
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// so we want to avoid computing the address twice.
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for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
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UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
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if (UI->getOpcode() == ISD::CopyToReg) {
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MatchAddressBase(Addr, AM);
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Done = true;
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break;
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}
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}
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}
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}
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if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
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return false;
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DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
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MVT VT = Addr.getValueType();
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if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
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if (!AM.Base.Reg.getNode())
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AM.Base.Reg = CurDAG->getRegister(0, VT);
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}
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assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
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getAddressOperandsRI(AM, Base, Disp);
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return true;
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}
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/// Returns true if the address can be represented by a base register plus
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/// index register plus an unsigned 12-bit displacement [base + idx + imm].
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bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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SystemZRRIAddressMode AM20, AM12;
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SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
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bool Done = false;
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if (!Addr.hasOneUse()) {
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@ -351,6 +351,9 @@ SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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case SystemZ::MOV64m32r:
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Opc = SystemZ::MOV64m32ry;
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break;
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case SystemZ::MOV8mi:
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Opc = SystemZ::MOV8miy;
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break;
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case SystemZ::MUL32rm:
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Opc = SystemZ::MUL32rmy;
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break;
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@ -244,22 +244,24 @@ def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
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"stg\t{$src, $dst}",
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[(store GR64:$src, rriaddr:$dst)]>;
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// FIXME: displacements here are really 12 bit, not 20!
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def MOV8mi : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
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def MOV8mi : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src),
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"mvi\t{$dst, $src}",
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[(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
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def MOV8miy : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
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"mviy\t{$dst, $src}",
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[(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
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def MOV16mi : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
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def MOV16mi : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src),
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"mvhhi\t{$dst, $src}",
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[(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>,
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[(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
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Requires<[IsZ10]>;
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def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
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def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src),
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"mvhi\t{$dst, $src}",
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[(store (i32 immSExt16:$src), riaddr:$dst)]>,
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[(store (i32 immSExt16:$src), riaddr12:$dst)]>,
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Requires<[IsZ10]>;
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def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
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def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src),
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"mvghi\t{$dst, $src}",
|
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[(store (i64 immSExt16:$src), riaddr:$dst)]>,
|
||||
[(store (i64 immSExt16:$src), riaddr12:$dst)]>,
|
||||
Requires<[IsZ10]>;
|
||||
|
||||
// sexts
|
||||
|
||||
@ -252,11 +252,17 @@ def s32imm64 : Operand<i64> {
|
||||
|
||||
// riaddr := reg + imm
|
||||
def riaddr32 : Operand<i32>,
|
||||
ComplexPattern<i32, 2, "SelectAddrRI32", []> {
|
||||
ComplexPattern<i32, 2, "SelectAddrRI12", []> {
|
||||
let PrintMethod = "printRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
|
||||
}
|
||||
|
||||
def riaddr12 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrRI12", []> {
|
||||
let PrintMethod = "printRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp);
|
||||
}
|
||||
|
||||
def riaddr : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrRI", []> {
|
||||
let PrintMethod = "printRIAddrOperand";
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvghi | count 1
|
||||
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvhi | count 1
|
||||
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvhhi | count 1
|
||||
; RUN: llvm-as < %s | llc | grep mvi | count 1
|
||||
; RUN: llvm-as < %s | llc | grep mvi | count 2
|
||||
; RUN: llvm-as < %s | llc | grep mviy | count 1
|
||||
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
|
||||
target triple = "s390x-unknown-linux-gnu"
|
||||
@ -33,3 +34,17 @@ entry:
|
||||
store i8 4, i8* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo5(i8* nocapture %a, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i8* %a, i64 -1 ; <i8*> [#uses=1]
|
||||
store i8 4, i8* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo6(i16* nocapture %a, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i16* %a, i64 -1 ; <i16*> [#uses=1]
|
||||
store i16 3, i16* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user