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[ARM] More aggressive matching for vpadd and vpaddl.
The new matchers work after legalization to make them simpler, and to avoid blocking other optimizations. Differential Revision: https://reviews.llvm.org/D27779 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
8672808b6b
commit
1f1e5c29c3
@ -9227,12 +9227,102 @@ SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
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return SDValue();
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}
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// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
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// (only after legalization).
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static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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static bool IsVUZPShuffleNode(SDNode *N) {
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// VUZP shuffle node.
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if (N->getOpcode() == ARMISD::VUZP)
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return true;
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// "VUZP" on i32 is an alias for VTRN.
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if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32)
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return true;
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return false;
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}
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static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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// Look for ADD(VUZP.0, VUZP.1).
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if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() ||
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N0 == N1)
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return SDValue();
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// Make sure the ADD is a 64-bit add; there is no 128-bit VPADD.
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if (!N->getValueType(0).is64BitVector())
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return SDValue();
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// Generate vpadd.
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDLoc dl(N);
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SDNode *Unzip = N0.getNode();
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EVT VT = N->getValueType(0);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpadd, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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Ops.push_back(Unzip->getOperand(0));
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Ops.push_back(Unzip->getOperand(1));
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
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}
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static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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// Check for two extended operands.
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if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
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N1.getOpcode() == ISD::SIGN_EXTEND) &&
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!(N0.getOpcode() == ISD::ZERO_EXTEND &&
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N1.getOpcode() == ISD::ZERO_EXTEND))
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return SDValue();
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SDValue N00 = N0.getOperand(0);
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SDValue N10 = N1.getOperand(0);
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// Look for ADD(SEXT(VUZP.0), SEXT(VUZP.1))
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if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() ||
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N00 == N10)
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return SDValue();
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// We only recognize Q register paddl here; this can't be reached until
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// after type legalization.
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if (!N00.getValueType().is64BitVector() ||
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!N0.getValueType().is128BitVector())
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return SDValue();
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// Generate vpaddl.
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDLoc dl(N);
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EVT VT = N->getValueType(0);
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SmallVector<SDValue, 8> Ops;
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// Form vpaddl.sN or vpaddl.uN depending on the kind of extension.
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unsigned Opcode;
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if (N0.getOpcode() == ISD::SIGN_EXTEND)
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Opcode = Intrinsic::arm_neon_vpaddls;
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else
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Opcode = Intrinsic::arm_neon_vpaddlu;
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Ops.push_back(DAG.getConstant(Opcode, dl,
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TLI.getPointerTy(DAG.getDataLayout())));
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EVT ElemTy = N00.getValueType().getVectorElementType();
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unsigned NumElts = VT.getVectorNumElements();
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EVT ConcatVT = EVT::getVectorVT(*DAG.getContext(), ElemTy, NumElts * 2);
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SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT,
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N00.getOperand(0), N00.getOperand(1));
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Ops.push_back(Concat);
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
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}
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// FIXME: This function shouldn't be necessary; if we lower BUILD_VECTOR in
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// an appropriate manner, we end up with ADD(VUZP(ZEXT(N))), which is
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// much easier to match.
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static SDValue
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AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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// Only perform optimization if after legalize, and if NEON is available. We
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// also expected both operands to be BUILD_VECTORs.
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if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
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@ -9288,6 +9378,10 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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return SDValue();
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}
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// Don't generate vpaddl+vmovn; we'll match it to vpadd later.
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if (Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
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return SDValue();
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// Create VPADDL node.
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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@ -9559,9 +9653,15 @@ static SDValue PerformADDCCombine(SDNode *N,
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static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget){
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// Attempt to create vpadd for this add.
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if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
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return Result;
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// Attempt to create vpaddl for this add.
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if (SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget))
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if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
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return Result;
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if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
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Subtarget))
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return Result;
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// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
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@ -214,14 +214,11 @@ define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
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}
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; Combine vuzp+vadd->vpadd.
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; FIXME: Implement this optimization
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define void @addCombineToVPADD(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADD:
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define void @addCombineToVPADD_i8(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADD_i8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vorr d18, d17, d17
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; CHECK-NEXT: vuzp.8 d16, d18
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; CHECK-NEXT: vadd.i8 d16, d18, d16
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; CHECK-NEXT: vpadd.i8 d16, d16, d17
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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@ -233,15 +230,44 @@ define void @addCombineToVPADD(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp {
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ret void
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}
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; Combine vuzp+vaddl->vpaddl
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; FIXME: Implement this optimization.
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define void @addCombineToVPADDL_sext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDL_sext:
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; Combine vuzp+vadd->vpadd.
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define void @addCombineToVPADD_i16(<8 x i16> *%cbcr, <4 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADD_i16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vorr d18, d17, d17
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; CHECK-NEXT: vuzp.8 d16, d18
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; CHECK-NEXT: vaddl.s8 q8, d18, d16
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; CHECK-NEXT: vpadd.i16 d16, d16, d17
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <8 x i16>, <8 x i16>* %cbcr
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%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%add = add <4 x i16> %tmp3, %tmp1
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store <4 x i16> %add, <4 x i16>* %X, align 8
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ret void
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}
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; Combine vtrn+vadd->vpadd.
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define void @addCombineToVPADD_i32(<4 x i32> *%cbcr, <2 x i32> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADD_i32:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vpadd.i32 d16, d16, d17
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <4 x i32>, <4 x i32>* %cbcr
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%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
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%add = add <2 x i32> %tmp3, %tmp1
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store <2 x i32> %add, <2 x i32>* %X, align 8
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ret void
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}
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; Combine vuzp+vaddl->vpaddl
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define void @addCombineToVPADDLq_s8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDLq_s8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vpaddl.s8 q8, q8
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; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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@ -254,10 +280,200 @@ define void @addCombineToVPADDL_sext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind s
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ret void
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}
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; Legalization produces a EXTRACT_VECTOR_ELT DAG node which performs an extend from
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; i16 to i32. In this case the input for the formed VPADDL needs to be a vector of i16s.
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define <2 x i16> @fromExtendingExtractVectorElt(<4 x i16> %in) {
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; CHECK-LABEL: fromExtendingExtractVectorElt:
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; Combine vuzp+vaddl->vpaddl
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; FIXME: Legalization butchers the shuffles.
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define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDL_s8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vmov.i16 d18, #0x8
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; CHECK-NEXT: vneg.s16 d18, d18
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; CHECK-NEXT: vext.8 d19, d16, d16, #1
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; CHECK-NEXT: vshl.i16 d16, d16, #8
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; CHECK-NEXT: vshl.i16 d17, d19, #8
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; CHECK-NEXT: vshl.s16 d16, d16, d18
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; CHECK-NEXT: vshl.s16 d17, d17, d18
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; CHECK-NEXT: vadd.i16 d16, d17, d16
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp4 = sext <4 x i8> %tmp3 to <4 x i16>
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%tmp5 = sext <4 x i8> %tmp1 to <4 x i16>
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%add = add <4 x i16> %tmp4, %tmp5
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store <4 x i16> %add, <4 x i16>* %X, align 8
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ret void
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}
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; Combine vuzp+vaddl->vpaddl
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define void @addCombineToVPADDLq_u8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDLq_u8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vpaddl.u8 q8, q8
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; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
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%tmp5 = zext <8 x i8> %tmp1 to <8 x i16>
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%add = add <8 x i16> %tmp4, %tmp5
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store <8 x i16> %add, <8 x i16>* %X, align 8
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ret void
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}
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; In theory, it's possible to match this to vpaddl, but rearranging the
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; shuffle is awkward, so this doesn't match at the moment.
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define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDLq_u8_early_zext:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vmovl.u8 q9, d17
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; CHECK-NEXT: vmovl.u8 q8, d16
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; CHECK-NEXT: vuzp.16 q8, q9
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; CHECK-NEXT: vadd.i16 q8, q8, q9
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; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = zext <16 x i8> %tmp to <16 x i16>
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%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%add = add <8 x i16> %tmp2, %tmp3
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store <8 x i16> %add, <8 x i16>* %X, align 8
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ret void
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}
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; Combine vuzp+vaddl->vpaddl
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; FIXME: Legalization butchers the shuffle.
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define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDL_u8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vext.8 d18, d16, d16, #1
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; CHECK-NEXT: vbic.i16 d16, #0xff00
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; CHECK-NEXT: vbic.i16 d18, #0xff00
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; CHECK-NEXT: vadd.i16 d16, d18, d16
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp4 = zext <4 x i8> %tmp3 to <4 x i16>
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%tmp5 = zext <4 x i8> %tmp1 to <4 x i16>
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%add = add <4 x i16> %tmp4, %tmp5
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store <4 x i16> %add, <4 x i16>* %X, align 8
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ret void
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}
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; Matching to vpaddl.8 requires matching shuffle(zext()).
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define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDL_u8_early_zext:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vmovl.u8 q8, d16
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; CHECK-NEXT: vpadd.i16 d16, d16, d17
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = zext <16 x i8> %tmp to <16 x i16>
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%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%add = add <4 x i16> %tmp2, %tmp3
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store <4 x i16> %add, <4 x i16>* %X, align 8
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ret void
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}
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; Combine vuzp+vaddl->vpaddl
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define void @addCombineToVPADDLq_s16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
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; CHECK-LABEL: addCombineToVPADDLq_s16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
|
||||
; CHECK-NEXT: vpaddl.s16 q8, q8
|
||||
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp = load <8 x i16>, <8 x i16>* %cbcr
|
||||
%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
||||
%tmp4 = sext <4 x i16> %tmp3 to <4 x i32>
|
||||
%tmp5 = sext <4 x i16> %tmp1 to <4 x i32>
|
||||
%add = add <4 x i32> %tmp4, %tmp5
|
||||
store <4 x i32> %add, <4 x i32>* %X, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Combine vuzp+vaddl->vpaddl
|
||||
define void @addCombineToVPADDLq_u16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
|
||||
; CHECK-LABEL: addCombineToVPADDLq_u16:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
|
||||
; CHECK-NEXT: vpaddl.u16 q8, q8
|
||||
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp = load <8 x i16>, <8 x i16>* %cbcr
|
||||
%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
||||
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
|
||||
%tmp5 = zext <4 x i16> %tmp1 to <4 x i32>
|
||||
%add = add <4 x i32> %tmp4, %tmp5
|
||||
store <4 x i32> %add, <4 x i32>* %X, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Combine vtrn+vaddl->vpaddl
|
||||
define void @addCombineToVPADDLq_s32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
|
||||
; CHECK-LABEL: addCombineToVPADDLq_s32:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
|
||||
; CHECK-NEXT: vpaddl.s32 q8, q8
|
||||
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp = load <4 x i32>, <4 x i32>* %cbcr
|
||||
%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
|
||||
%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
|
||||
%tmp4 = sext <2 x i32> %tmp3 to <2 x i64>
|
||||
%tmp5 = sext <2 x i32> %tmp1 to <2 x i64>
|
||||
%add = add <2 x i64> %tmp4, %tmp5
|
||||
store <2 x i64> %add, <2 x i64>* %X, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Combine vtrn+vaddl->vpaddl
|
||||
define void @addCombineToVPADDLq_u32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
|
||||
; CHECK-LABEL: addCombineToVPADDLq_u32:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
|
||||
; CHECK-NEXT: vpaddl.u32 q8, q8
|
||||
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp = load <4 x i32>, <4 x i32>* %cbcr
|
||||
%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
|
||||
%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
|
||||
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
|
||||
%tmp5 = zext <2 x i32> %tmp1 to <2 x i64>
|
||||
%add = add <2 x i64> %tmp4, %tmp5
|
||||
store <2 x i64> %add, <2 x i64>* %X, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Legalization promotes the <4 x i8> to <4 x i16>.
|
||||
define <4 x i8> @fromExtendingExtractVectorElt_i8(<8 x i8> %in) {
|
||||
; CHECK-LABEL: fromExtendingExtractVectorElt_i8:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vmov d16, r0, r1
|
||||
; CHECK-NEXT: vpaddl.s8 d16, d16
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = shufflevector <8 x i8> %in, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%tmp2 = shufflevector <8 x i8> %in, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
||||
%x = add <4 x i8> %tmp2, %tmp1
|
||||
ret <4 x i8> %x
|
||||
}
|
||||
|
||||
; Legalization promotes the <2 x i16> to <2 x i32>.
|
||||
define <2 x i16> @fromExtendingExtractVectorElt_i16(<4 x i16> %in) {
|
||||
; CHECK-LABEL: fromExtendingExtractVectorElt_i16:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vmov d16, r0, r1
|
||||
; CHECK-NEXT: vpaddl.s16 d16, d16
|
||||
|
||||
@ -70,14 +70,14 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
; CHECK-NEXT: vldr d16, [r1]
|
||||
; CHECK-NEXT: vldr d17, [r0]
|
||||
; CHECK-NEXT: vtrn.32 d17, d16
|
||||
; CHECK-NEXT: vadd.i32 d16, d17, d16
|
||||
; CHECK-NEXT: vmul.i32 d16, d17, d16
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <2 x i32>, <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>, <2 x i32>* %B
|
||||
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
|
||||
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
|
||||
%tmp5 = add <2 x i32> %tmp3, %tmp4
|
||||
%tmp5 = mul <2 x i32> %tmp3, %tmp4
|
||||
ret <2 x i32> %tmp5
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user