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[Hexagon] Remove the remnants of isConstExtProfitable

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2015-10-20 19:04:53 +00:00
parent 70f8c2049f
commit 1f2d4d356d
7 changed files with 32 additions and 130 deletions
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2
lib/Target/Hexagon/Hexagon.td
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@ -161,7 +161,7 @@ def getNonNVStore : InstrMapping {
def getBasedWithImmOffset : InstrMapping {
let FilterClass = "AddrModeRel";
let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
"isMEMri", "isFloat"];
"isFloat"];
let ColFields = ["addrMode"];
let KeyCol = ["Absolute"];
let ValueCols = [["BaseImmOffset"]];

14
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -104,7 +104,6 @@ public:
SDNode *SelectConstantFP(SDNode *N);
SDNode *SelectAdd(SDNode *N);
SDNode *SelectBitOp(SDNode *N);
bool isConstExtProfitable(SDNode *N) const;
// XformMskToBitPosU5Imm - Returns the bit position which
// the single bit 32 bit mask represents.
@ -1328,19 +1327,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
return false;
}
bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
unsigned UseCount = 0;
unsigned CallCount = 0;
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
// Ignore call instructions.
if (I->getOpcode() == ISD::CopyToReg)
++CallCount;
UseCount++;
}
return (UseCount <= 1) || (CallCount > 1);
}
void HexagonDAGToDAGISel::PreprocessISelDAG() {
SelectionDAG &DAG = *CurDAG;

1
lib/Target/Hexagon/HexagonInstrFormats.td
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@ -188,7 +188,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
string PNewValue = "";
string NValueST = ""; // Set to "true" for new-value stores.
string InputType = ""; // Input is "imm" or "reg" type.
string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
string isFloat = "false"; // Set to "true" for the floating-point load/store.
string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions

4
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -2825,7 +2825,7 @@ let CextOpcode = "ADD_acc" in {
let isExtentSigned = 1 in
def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
[(set (i32 IntRegs:$dst),
(add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3),
(add (add (i32 IntRegs:$src2), s32ImmPred:$src3),
(i32 IntRegs:$src1)))]>, ImmRegRel;
def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
@ -2859,7 +2859,7 @@ class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>;
def : T_MType_acc_pat1 <M2_naccii, add, sub, s16_16ImmPred>;
def : T_MType_acc_pat1 <M2_naccii, add, sub, s32ImmPred>;
def : T_MType_acc_pat2 <M2_nacci, add, sub>;
//===----------------------------------------------------------------------===//

2
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -1903,7 +1903,7 @@ def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
(ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
"$Rd = add($Rs, add($Ru, #$s6))" ,
[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
(add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
(add (i32 IntRegs:$Ru), s32ImmPred:$s6)))],
"", ALU64_tc_2_SLOT23> {
bits<5> Rd;
bits<5> Rs;

22
lib/Target/Hexagon/HexagonIntrinsics.td
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@ -691,15 +691,15 @@ def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32ImmPred, s8ImmPred>;
def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
(i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
// Mux
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32ImmPred>;
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32ImmPred>;
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32ImmPred, s8ImmPred>;
// Shift halfword
def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
@ -720,17 +720,17 @@ def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32ImmPred>;
def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32ImmPred>;
def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32ImmPred>;
def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s32ImmPred:$src2)),
(i32 (C2_cmpgti (I32:$src1),
(DEC_CONST_SIGNED s8ExtPred:$src2)))>;
(DEC_CONST_SIGNED s32ImmPred:$src2)))>;
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u32ImmPred:$src2)),
(i32 (C2_cmpgtui (I32:$src1),
(DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
(DEC_CONST_UNSIGNED u32ImmPred:$src2)))>;
// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),

117
lib/Target/Hexagon/HexagonOperands.td
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@ -96,32 +96,12 @@ def s31_1ImmPred : PatLeaf<(i32 imm), [{
def s30_2ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<31,1>(v);
return isShiftedInt<30,2>(v);
}]>;
def s29_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<31,1>(v);
}]>;
def s22_10ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<22,10>(v);
}]>;
def s8_24ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<8,24>(v);
}]>;
def s16_16ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<16,16>(v);
}]>;
def s26_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<26,6>(v);
return isShiftedInt<29,3>(v);
}]>;
def s16ImmPred : PatLeaf<(i32 imm), [{
@ -129,16 +109,6 @@ def s16ImmPred : PatLeaf<(i32 imm), [{
return isInt<16>(v);
}]>;
def s13ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<13>(v);
}]>;
def s12ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<12>(v);
}]>;
def s11_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<11>(v);
@ -164,16 +134,6 @@ def s10ImmPred : PatLeaf<(i32 imm), [{
return isInt<10>(v);
}]>;
def s9ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<9>(v);
}]>;
def m9ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<9>(v) && (v != -256);
}]>;
def s8ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<8>(v);
@ -245,21 +205,21 @@ def u26_6ImmPred : PatLeaf<(i32 imm), [{
return isShiftedUInt<26,6>(v);
}]>;
def u16ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<16>(v);
}]>;
def u16_s8ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<16,8>(v);
}]>;
def u16_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<16>(v);
}]>;
def u16_1ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<16,1>(v);
}]>;
def u16_2ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<16,2>(v);
}]>;
def u11_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<11,3>(v);
@ -394,7 +354,7 @@ def Clr5ImmPred : PatLeaf<(i32 imm), [{
}]>;
def SetClr5ImmPred : PatLeaf<(i32 imm), [{
// SetClr5ImmPred predicate - True if the immediate is in range 0..31.
// True if the immediate is in range 0..31.
int32_t v = (int32_t)N->getSExtValue();
return (v >= 0 && v <= 31);
}]>;
@ -419,14 +379,13 @@ def Clr4ImmPred : PatLeaf<(i32 imm), [{
}]>;
def SetClr4ImmPred : PatLeaf<(i32 imm), [{
// SetClr4ImmPred predicate - True if the immediate is in the range 0..15.
// True if the immediate is in the range 0..15.
int16_t v = (int16_t)N->getSExtValue();
return (v >= 0 && v <= 15);
}]>;
def Set3ImmPred : PatLeaf<(i32 imm), [{
// Set3ImmPred predicate - True if the number is in the series of values:
// [ 2^0, 2^1, ... 2^7 ].
// True if the number is in the series of values: [ 2^0, 2^1, ... 2^7 ].
// For use in setbit immediate.
uint8_t v = (int8_t)N->getSExtValue();
// Constrain to 8 bits, and then check for single bit.
@ -434,9 +393,7 @@ def Set3ImmPred : PatLeaf<(i32 imm), [{
}]>;
def Clr3ImmPred : PatLeaf<(i32 imm), [{
// Clr3ImmPred predicate - True if the number is in the series of
// bit negated values:
// [ 2^0, 2^1, ... 2^7 ].
// True if the number is in the series of bit negated values: [ 2^0, 2^1, ... 2^7 ].
// For use in setbit and clrbit immediate.
uint8_t v = ~ (int8_t)N->getSExtValue();
// Constrain to 8 bits, and then check for single bit.
@ -444,7 +401,7 @@ def Clr3ImmPred : PatLeaf<(i32 imm), [{
}]>;
def SetClr3ImmPred : PatLeaf<(i32 imm), [{
// SetClr3ImmPred predicate - True if the immediate is in the range 0..7.
// True if the immediate is in the range 0..7.
int8_t v = (int8_t)N->getSExtValue();
return (v >= 0 && v <= 7);
}]>;
@ -476,46 +433,6 @@ let PrintMethod = "printExtOperand" in {
def u6_3Ext : Operand<i32>;
}
def s10ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (isInt<10>(v))
return true;
// Return true if extending this immediate is profitable and the value
// can fit in a 32-bit signed field.
return isConstExtProfitable(Node) && isInt<32>(v);
}]>;
def s8ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (isInt<8>(v))
return true;
// Return true if extending this immediate is profitable and the value
// can fit in a 32-bit signed field.
return isConstExtProfitable(Node) && isInt<32>(v);
}]>;
def u8ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (isUInt<8>(v))
return true;
// Return true if extending this immediate is profitable and the value
// can fit in a 32-bit unsigned field.
return isConstExtProfitable(Node) && isUInt<32>(v);
}]>;
def u9ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (isUInt<9>(v))
return true;
// Return true if extending this immediate is profitable and the value
// can fit in a 32-bit unsigned field.
return isConstExtProfitable(Node) && isUInt<32>(v);
}]>;
def s4_7ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();