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Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -416,8 +416,11 @@ def pclabel : Operand<i32> {
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}
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// ADR instruction labels.
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def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
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def adrlabel : Operand<i32> {
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let EncoderMethod = "getAdrLabelOpValue";
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let ParserMatchClass = AdrLabelAsmOperand;
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let PrintMethod = "printAdrLabelOperand";
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}
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def neon_vcvt_imm32 : Operand<i32> {
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@ -172,6 +172,7 @@ def t2ldr_pcrel_imm12 : Operand<i32> {
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// ADR instruction labels.
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def t2adrlabel : Operand<i32> {
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let EncoderMethod = "getT2AdrLabelOpValue";
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let PrintMethod = "printAdrLabelOperand";
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}
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@ -796,6 +796,13 @@ public:
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int64_t Value = CE->getValue();
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return Value > 0 && Value <= 32;
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}
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bool isAdrLabel() const {
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// If we have an immediate that's not a constant, treat it as a label
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// reference needing a fixup. If it is a constant, but it can't fit
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// into shift immediate encoding, we reject it.
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if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
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else return (isARMSOImm() || isARMSOImmNeg());
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}
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bool isARMSOImm() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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@ -1644,6 +1651,22 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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assert(isImm() && "Not an immediate!");
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// If we have an immediate that's not a constant, treat it as a label
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// reference needing a fixup.
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if (!isa<MCConstantExpr>(getImm())) {
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Inst.addOperand(MCOperand::CreateExpr(getImm()));
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return;
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}
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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int Val = CE->getValue();
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
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@ -792,6 +792,25 @@ void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
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llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
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}
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void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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if (MO.isExpr()) {
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O << *MO.getExpr();
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return;
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}
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int32_t OffImm = (int32_t)MO.getImm();
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if (OffImm == INT32_MIN)
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O << "#-0";
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else if (OffImm < 0)
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O << "#-" << -OffImm;
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else
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O << "#" << OffImm;
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}
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void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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O << "#" << MI->getOperand(OpNum).getImm() * 4;
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@ -73,6 +73,7 @@ public:
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void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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@ -641,8 +641,8 @@ getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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return Val;
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}
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/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
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/// target.
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/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
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/// ADR label target.
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uint32_t ARMMCCodeEmitter::
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getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -652,15 +652,23 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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Fixups);
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int32_t offset = MO.getImm();
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uint32_t Val = 0x2000;
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if (offset < 0) {
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if (offset == INT32_MIN) {
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Val = 0x1000;
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offset = 0;
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} else if (offset < 0) {
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Val = 0x1000;
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offset *= -1;
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}
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Val |= offset;
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int SoImmVal = ARM_AM::getSOImmVal(offset);
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assert(SoImmVal != -1 && "Not a valid so_imm value!");
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Val |= SoImmVal;
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return Val;
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}
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/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
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/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
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/// target.
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uint32_t ARMMCCodeEmitter::
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getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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@ -670,14 +678,16 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
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Fixups);
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int32_t Val = MO.getImm();
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if (Val < 0) {
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if (Val == INT32_MIN)
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Val = 0x1000;
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else if (Val < 0) {
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Val *= -1;
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Val |= 0x1000;
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}
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return Val;
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}
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/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
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/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
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/// target.
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uint32_t ARMMCCodeEmitter::
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getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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@ -141,6 +141,14 @@ Lforward:
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@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2]
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@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2]
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adr r1, #-0x0
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adr r1, #-0x12000000
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adr r1, #0x12000000
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@ CHECK: adr r1, #-0 @ encoding: [0x00,0x10,0x4f,0xe2]
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@ CHECK: adr r1, #-301989888 @ encoding: [0x12,0x14,0x4f,0xe2]
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@ CHECK: adr r1, #301989888 @ encoding: [0x12,0x14,0x8f,0xe2]
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@------------------------------------------------------------------------------
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@ ADD
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@ -135,9 +135,11 @@ _func:
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subw r11, pc, #3270
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adr.w r11, #-826
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adr.w r1, #-0x0
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@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b]
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@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b]
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@ CHECK: adr.w r1, #-0 @ encoding: [0xaf,0xf2,0x00,0x01]
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@------------------------------------------------------------------------------
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@ AND (immediate)
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@ -169,9 +169,15 @@
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#------------------------------------------------------------------------------
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# CHECK: add r2, pc, #3
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# CHECK: sub r2, pc, #3
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# CHECK: sub r1, pc, #0
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# CHECK: sub r1, pc, #301989888
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# CHECK: add r1, pc, #301989888
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0x03 0x20 0x8f 0xe2
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0x03 0x20 0x4f 0xe2
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0x00 0x10 0x4f 0xe2
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0x12 0x14 0x4f 0xe2
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0x12 0x14 0x8f 0xe2
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#------------------------------------------------------------------------------
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# AND
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@ -92,9 +92,11 @@
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#------------------------------------------------------------------------------
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# CHECK: subw r11, pc, #3270
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# CHECK: subw r11, pc, #826
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# CHECK: subw r1, pc, #0
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0xaf 0xf6 0xc6 0x4b
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0xaf 0xf2 0x3a 0x3b
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0xaf 0xf2 0x00 0x01
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#------------------------------------------------------------------------------
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# AND (immediate)
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