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[SystemZ] Extend RISBG optimization

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The handling of ANY_EXTEND and ZERO_EXTEND was too strict.  In this context
we can treat ZERO_EXTEND in much the same way as an AND and then also handle
outermost ZERO_EXTENDs.

I couldn't find a test that benefited from the ANY_EXTEND change, but it's
more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are
handled differently.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-12-20 11:49:48 +00:00
parent 78a613731e
commit 1fd4e55828
2 changed files with 30 additions and 5 deletions
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20
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -764,9 +764,22 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
return true;
}
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND: {
case ISD::ANY_EXTEND:
// Bits above the extended operand are don't-care.
RxSBG.Input = N.getOperand(0);
return true;
case ISD::ZERO_EXTEND: {
// Restrict the mask to the extended operand.
unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
return false;
RxSBG.Input = N.getOperand(0);
return true;
}
case ISD::SIGN_EXTEND: {
// Check that the extension bits are don't-care (i.e. are masked out
// by the final mask).
unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
@ -1064,6 +1077,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
case ISD::ROTL:
case ISD::SHL:
case ISD::SRL:
case ISD::ZERO_EXTEND:
if (!ResNode)
ResNode = tryRISBGZero(Node);
break;

15
test/CodeGen/SystemZ/risbg-01.ll
View File

@ -457,11 +457,22 @@ define i64 @f40(i64 %foo, i64 *%dest) {
ret i64 %and
}
; Check a case where the result is zero-extended.
define i64 @f41(i32 %a) {
; CHECK-LABEL: f41
; CHECK: risbg %r2, %r2, 36, 191, 62
; CHECK: br %r14
%shl = shl i32 %a, 2
%shr = lshr i32 %shl, 4
%ext = zext i32 %shr to i64
ret i64 %ext
}
; In this case the sign extension is converted to a pair of 32-bit shifts,
; which is then extended to 64 bits. We previously used the wrong bit size
; when testing whether the shifted-in bits of the shift right were significant.
define i64 @f41(i1 %x) {
; CHECK-LABEL: f41:
define i64 @f42(i1 %x) {
; CHECK-LABEL: f42:
; CHECK: sll %r2, 31
; CHECK: sra %r2, 31
; CHECK: llgcr %r2, %r2