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[x86] add negate-i1 run for 32-bit target

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2016-10-13 14:27:08 +00:00
parent 262bc1134d
commit 2061c51e0e
1 changed files with 112 additions and 51 deletions
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163
test/CodeGen/X86/negate-i1.ll
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@ -1,99 +1,160 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
define i8 @select_i8_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i8_neg1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: shlb $7, %dil
; CHECK-NEXT: sarb $7, %dil
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
; X64-LABEL: select_i8_neg1_or_0:
; X64: # BB#0:
; X64-NEXT: shlb $7, %dil
; X64-NEXT: sarb $7, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
;
; X32-LABEL: select_i8_neg1_or_0:
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: shlb $7, %al
; X32-NEXT: sarb $7, %al
; X32-NEXT: retl
;
%b = sext i1 %a to i8
ret i8 %b
}
define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
; CHECK-LABEL: select_i8_neg1_or_0_zeroext:
; CHECK: # BB#0:
; CHECK-NEXT: shlb $7, %dil
; CHECK-NEXT: sarb $7, %dil
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
; X64-LABEL: select_i8_neg1_or_0_zeroext:
; X64: # BB#0:
; X64-NEXT: shlb $7, %dil
; X64-NEXT: sarb $7, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
;
; X32-LABEL: select_i8_neg1_or_0_zeroext:
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: shlb $7, %al
; X32-NEXT: sarb $7, %al
; X32-NEXT: retl
;
%b = sext i1 %a to i8
ret i8 %b
}
define i16 @select_i16_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i16_neg1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: shll $15, %edi
; CHECK-NEXT: sarw $15, %di
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
; X64-LABEL: select_i16_neg1_or_0:
; X64: # BB#0:
; X64-NEXT: shll $15, %edi
; X64-NEXT: sarw $15, %di
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
;
; X32-LABEL: select_i16_neg1_or_0:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $15, %eax
; X32-NEXT: sarw $15, %ax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
%b = sext i1 %a to i16
ret i16 %b
}
define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
; CHECK-LABEL: select_i16_neg1_or_0_zeroext:
; CHECK: # BB#0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: shll $15, %eax
; CHECK-NEXT: sarw $15, %ax
; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; CHECK-NEXT: retq
; X64-LABEL: select_i16_neg1_or_0_zeroext:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: shll $15, %eax
; X64-NEXT: sarw $15, %ax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
;
; X32-LABEL: select_i16_neg1_or_0_zeroext:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $15, %eax
; X32-NEXT: sarw $15, %ax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
%b = sext i1 %a to i16
ret i16 %b
}
define i32 @select_i32_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i32_neg1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: shll $31, %edi
; CHECK-NEXT: sarl $31, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
; X64-LABEL: select_i32_neg1_or_0:
; X64: # BB#0:
; X64-NEXT: shll $31, %edi
; X64-NEXT: sarl $31, %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
;
; X32-LABEL: select_i32_neg1_or_0:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $31, %eax
; X32-NEXT: sarl $31, %eax
; X32-NEXT: retl
;
%b = sext i1 %a to i32
ret i32 %b
}
define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
; CHECK: # BB#0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: shll $31, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: retq
; X64-LABEL: select_i32_neg1_or_0_zeroext:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: shll $31, %eax
; X64-NEXT: sarl $31, %eax
; X64-NEXT: retq
;
; X32-LABEL: select_i32_neg1_or_0_zeroext:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $31, %eax
; X32-NEXT: sarl $31, %eax
; X32-NEXT: retl
;
%b = sext i1 %a to i32
ret i32 %b
}
define i64 @select_i64_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i64_neg1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; CHECK-NEXT: shlq $63, %rdi
; CHECK-NEXT: sarq $63, %rdi
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
; X64-LABEL: select_i64_neg1_or_0:
; X64: # BB#0:
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: shlq $63, %rdi
; X64-NEXT: sarq $63, %rdi
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
;
; X32-LABEL: select_i64_neg1_or_0:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $31, %eax
; X32-NEXT: sarl $31, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: retl
;
%b = sext i1 %a to i64
ret i64 %b
}
define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
; CHECK-LABEL: select_i64_neg1_or_0_zeroext:
; CHECK: # BB#0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: shlq $63, %rax
; CHECK-NEXT: sarq $63, %rax
; CHECK-NEXT: retq
; X64-LABEL: select_i64_neg1_or_0_zeroext:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: shlq $63, %rax
; X64-NEXT: sarq $63, %rax
; X64-NEXT: retq
;
; X32-LABEL: select_i64_neg1_or_0_zeroext:
; X32: # BB#0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $31, %eax
; X32-NEXT: sarl $31, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: retl
;
%b = sext i1 %a to i64
ret i64 %b