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[mips] Do not tail-call optimize vararg functions or functions with byval
arguments. This is rather conservative and should be fixed later to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166851 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2639,19 +2639,16 @@ static unsigned getNextIntArgReg(unsigned Reg) {
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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bool MipsTargetLowering::
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IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC,
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IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, bool IsVarArg,
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unsigned NextStackOffset) const {
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if (!EnableMipsTailCalls)
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return false;
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// Do not tail-call optimize if there is an argument passed on stack.
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if (IsO32 && (CalleeCC != CallingConv::Fast)) {
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if (NextStackOffset > 16)
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return false;
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} else if (NextStackOffset)
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if (MipsCCInfo.hasByValArg() || IsVarArg)
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return false;
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return true;
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// Return true if no arguments are passed on stack.
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return MipsCCInfo.reservedArgArea() == NextStackOffset;
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}
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/// LowerCall - functions arguments are copied from virtual regs to
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@ -2690,7 +2687,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Check if it's really possible to do a tail call.
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if (isTailCall)
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isTailCall = IsEligibleForTailCallOptimization(CallConv, NextStackOffset);
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isTailCall = IsEligibleForTailCallOptimization(MipsCCInfo, isVarArg,
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NextStackOffset);
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if (isTailCall)
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++NumTailCalls;
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@ -274,7 +274,8 @@ namespace llvm {
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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bool IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC,
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bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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bool IsVarArg,
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unsigned NextStackOffset) const;
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/// copyByValArg - Copy argument registers which were used to pass a byval
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@ -66,9 +66,15 @@ declare i32 @callee4(i32, i32, i32, i32, i32, i32, i32, i32, i32)
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define i32 @caller5() nounwind readonly {
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entry:
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; PIC32: .ent caller5
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; PIC32-NOT: jalr
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; PIC32: .end caller5
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; STATIC32: .ent caller5
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; STATIC32-NOT: jal
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; STATIC32: .end caller5
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; N64: .ent caller5
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; N64-NOT: jalr
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; N64: .end caller5
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%0 = load i32* @g0, align 4
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%1 = load i32* @g1, align 4
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@ -98,3 +104,55 @@ entry:
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ret i32 %add8
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}
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declare i32 @callee8(i32, ...)
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define i32 @caller8_0() nounwind {
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entry:
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%call = tail call fastcc i32 @caller8_1()
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ret i32 %call
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}
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define internal fastcc i32 @caller8_1() nounwind noinline {
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entry:
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; PIC32: .ent caller8_1
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; PIC32: jalr
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; PIC32: .end caller8_1
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; STATIC32: .ent caller8_1
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; STATIC32: jal
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; STATIC32: .end caller8_1
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; N64: .ent caller8_1
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; N64: jalr
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; N64: .end caller8_1
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%call = tail call i32 (i32, ...)* @callee8(i32 2, i32 1) nounwind
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ret i32 %call
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}
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%struct.S = type { [2 x i32] }
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@gs1 = external global %struct.S
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declare i32 @callee9(%struct.S* byval)
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define i32 @caller9_0() nounwind {
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entry:
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%call = tail call fastcc i32 @caller9_1()
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ret i32 %call
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}
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define internal fastcc i32 @caller9_1() nounwind noinline {
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entry:
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; PIC32: .ent caller9_1
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; PIC32: jalr
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; PIC32: .end caller9_1
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; STATIC32: .ent caller9_1
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; STATIC32: jal
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; STATIC32: .end caller9_1
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; N64: .ent caller9_1
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; N64: jalr
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; N64: .end caller9_1
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%call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
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ret i32 %call
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}
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