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ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
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Jim Grosbach
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541b2a4aa3
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22378fd664
@ -3634,7 +3634,7 @@ multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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}
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multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode> {
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string baseOpc, SDNode OpNode> {
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// 64-bit vector types.
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
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@ -3668,6 +3668,33 @@ multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
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OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
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// imm6 = xxxxxx
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// Aliases for two-operand forms (source and dest regs the same).
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "8 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i8"))
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DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "16 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i16"))
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DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "32 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v2i32"))
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DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "64 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v1i64"))
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DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "8 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v16i8"))
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QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "16 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i16"))
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QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "32 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i32"))
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QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "64 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v2i64"))
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QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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}
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// Neon Shift-Accumulate vector operations,
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@ -4606,8 +4633,10 @@ defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
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defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
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// VSHR : Vector Shift Right (Immediate)
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defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
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defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
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defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
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NEONvshrs>;
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defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
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NEONvshru>;
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// VSHLL : Vector Shift Left Long
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defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
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@ -4641,8 +4670,10 @@ defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vrshl", "u", int_arm_neon_vrshiftu>;
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// VRSHR : Vector Rounding Shift Right
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defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
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defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
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defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
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NEONvrshrs>;
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defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
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NEONvrshru>;
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// VRSHRN : Vector Rounding Shift Right and Narrow
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defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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@ -417,3 +417,73 @@ _foo:
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@ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2]
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@ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2]
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@ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2]
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@ Two-operand forms.
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vshr.s8 d15, #8
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vshr.s16 d12, #16
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vshr.s32 d13, #32
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vshr.s64 d14, #64
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vshr.u8 d16, #8
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vshr.u16 d17, #16
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vshr.u32 d6, #32
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vshr.u64 d10, #64
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vshr.s8 q1, #8
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vshr.s16 q2, #16
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vshr.s32 q3, #32
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vshr.s64 q4, #64
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vshr.u8 q5, #8
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vshr.u16 q6, #16
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vshr.u32 q7, #32
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vshr.u64 q8, #64
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@ CHECK: vshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf0,0x88,0xf2]
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@ CHECK: vshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc0,0x90,0xf2]
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@ CHECK: vshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd0,0xa0,0xf2]
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@ CHECK: vshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe0,0x80,0xf2]
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@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3]
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@ CHECK: vshr.u16 d17, d17, #16 @ encoding: [0x31,0x10,0xd0,0xf3]
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@ CHECK: vshr.u32 d6, d6, #32 @ encoding: [0x16,0x60,0xa0,0xf3]
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@ CHECK: vshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa0,0x80,0xf3]
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@ CHECK: vshr.s8 q1, q1, #8 @ encoding: [0x52,0x20,0x88,0xf2]
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@ CHECK: vshr.s16 q2, q2, #16 @ encoding: [0x54,0x40,0x90,0xf2]
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@ CHECK: vshr.s32 q3, q3, #32 @ encoding: [0x56,0x60,0xa0,0xf2]
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@ CHECK: vshr.s64 q4, q4, #64 @ encoding: [0xd8,0x80,0x80,0xf2]
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@ CHECK: vshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa0,0x88,0xf3]
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@ CHECK: vshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc0,0x90,0xf3]
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@ CHECK: vshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe0,0xa0,0xf3]
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@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3]
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vrshr.s8 d15, #8
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vrshr.s16 d12, #16
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vrshr.s32 d13, #32
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vrshr.s64 d14, #64
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vrshr.u8 d16, #8
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vrshr.u16 d17, #16
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vrshr.u32 d6, #32
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vrshr.u64 d10, #64
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vrshr.s8 q1, #8
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vrshr.s16 q2, #16
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vrshr.s32 q3, #32
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vrshr.s64 q4, #64
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vrshr.u8 q5, #8
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vrshr.u16 q6, #16
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vrshr.u32 q7, #32
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vrshr.u64 q8, #64
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@ CHECK: vrshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf2,0x88,0xf2]
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@ CHECK: vrshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc2,0x90,0xf2]
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@ CHECK: vrshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd2,0xa0,0xf2]
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@ CHECK: vrshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe2,0x80,0xf2]
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@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
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@ CHECK: vrshr.u16 d17, d17, #16 @ encoding: [0x31,0x12,0xd0,0xf3]
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@ CHECK: vrshr.u32 d6, d6, #32 @ encoding: [0x16,0x62,0xa0,0xf3]
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@ CHECK: vrshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa2,0x80,0xf3]
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@ CHECK: vrshr.s8 q1, q1, #8 @ encoding: [0x52,0x22,0x88,0xf2]
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@ CHECK: vrshr.s16 q2, q2, #16 @ encoding: [0x54,0x42,0x90,0xf2]
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@ CHECK: vrshr.s32 q3, q3, #32 @ encoding: [0x56,0x62,0xa0,0xf2]
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@ CHECK: vrshr.s64 q4, q4, #64 @ encoding: [0xd8,0x82,0x80,0xf2]
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@ CHECK: vrshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa2,0x88,0xf3]
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@ CHECK: vrshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc2,0x90,0xf3]
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@ CHECK: vrshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe2,0xa0,0xf3]
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@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
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