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R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200935 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -103,6 +103,11 @@ def IMM12bit : PatLeaf <(imm),
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[{return isUInt<12>(N->getZExtValue());}]
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>;
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def mubuf_vaddr_offset : PatFrag<
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(ops node:$ptr, node:$offset, node:$imm_offset),
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(add (add node:$ptr, node:$offset), node:$imm_offset)
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>;
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class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
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return
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(*(const SITargetLowering *)getTargetLowering()).analyzeImmediate(N) == 0;
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@ -1960,7 +1960,7 @@ defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
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multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
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PatFrag global_ld, PatFrag constant_ld> {
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def : Pat <
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(vt (global_ld (add (add i64:$ptr, i64:$offset), IMM12bit:$imm_offset))),
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(vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
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(Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
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>;
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@ -2006,6 +2006,11 @@ defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
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multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
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def : Pat <
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(st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
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(Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
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>;
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def : Pat <
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(st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
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(Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
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@ -84,3 +84,15 @@ entry:
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store i32 0, i32 addrspace(1)* %0
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ret void
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}
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; MUBUF store with a 12-bit immediate offset and a register offset
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; CHECK-LABEL: @mubuf_store3
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; CHECK-NOT: ADD
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; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4 ; encoding: [0x04,0x80
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define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) {
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entry:
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%0 = getelementptr i32 addrspace(1)* %out, i64 %offset
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%1 = getelementptr i32 addrspace(1)* %0, i64 1
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store i32 0, i32 addrspace(1)* %1
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ret void
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}
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