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Simplified BLEND pattern matching for shuffles.
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
eca1fcf3d2
commit
226e0e6264
@ -5641,64 +5641,53 @@ LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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DebugLoc dl = SVOp->getDebugLoc();
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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EVT VT = SVOp->getValueType(0);
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EVT EltVT = VT.getVectorElementType();
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unsigned NumElems = VT.getVectorNumElements();
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if (!Subtarget->hasSSE41())
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if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
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return SDValue();
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if (!Subtarget->hasInt256() && VT == MVT::v16i16)
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return SDValue();
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unsigned ISDNo = 0;
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MVT OpTy;
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// Check the mask for BLEND and build the value.
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unsigned MaskValue = 0;
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// There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
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unsigned NumLanes = (NumElems-1)/8 + 1;
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unsigned NumElemsInLane = NumElems / NumLanes;
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switch (VT.SimpleTy) {
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default: return SDValue();
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case MVT::v8i16:
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ISDNo = X86ISD::BLENDPW;
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OpTy = MVT::v8i16;
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break;
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case MVT::v4i32:
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case MVT::v4f32:
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ISDNo = X86ISD::BLENDPS;
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OpTy = MVT::v4f32;
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break;
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case MVT::v2i64:
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case MVT::v2f64:
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ISDNo = X86ISD::BLENDPD;
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OpTy = MVT::v2f64;
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break;
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case MVT::v8i32:
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case MVT::v8f32:
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if (!Subtarget->hasFp256())
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return SDValue();
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ISDNo = X86ISD::BLENDPS;
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OpTy = MVT::v8f32;
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break;
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case MVT::v4i64:
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case MVT::v4f64:
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if (!Subtarget->hasFp256())
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return SDValue();
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ISDNo = X86ISD::BLENDPD;
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OpTy = MVT::v4f64;
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break;
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}
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assert(ISDNo && "Invalid Op Number");
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// Blend for v16i16 should be symetric for the both lanes.
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for (unsigned i = 0; i < NumElemsInLane; ++i) {
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unsigned MaskVals = 0;
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for (unsigned i = 0; i != NumElems; ++i) {
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int SndLaneEltIdx = (NumLanes == 2) ?
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SVOp->getMaskElt(i + NumElemsInLane) : -1;
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int EltIdx = SVOp->getMaskElt(i);
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if (EltIdx == (int)i || EltIdx < 0)
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MaskVals |= (1<<i);
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else if (EltIdx == (int)(i + NumElems))
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continue; // Bit is set to zero;
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else
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if ((EltIdx == -1 || EltIdx == (int)i) &&
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(SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
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continue;
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if (((unsigned)EltIdx == (i + NumElems)) &&
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(SndLaneEltIdx == -1 ||
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(unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
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MaskValue |= (1<<i);
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else
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return SDValue();
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}
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V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
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V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
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SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
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DAG.getConstant(MaskVals, MVT::i32));
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// Convert i32 vectors to floating point if it is not AVX2.
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// AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
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EVT BlendVT = VT;
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if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
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BlendVT = EVT::getVectorVT(*DAG.getContext(),
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EVT::getFloatingPointVT(EltVT.getSizeInBits()),
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NumElems);
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V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
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V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
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}
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SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
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DAG.getConstant(MaskValue, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
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}
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@ -11972,9 +11961,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::ANDNP: return "X86ISD::ANDNP";
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case X86ISD::PSIGN: return "X86ISD::PSIGN";
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case X86ISD::BLENDV: return "X86ISD::BLENDV";
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case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
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case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
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case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
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case X86ISD::BLENDI: return "X86ISD::BLENDI";
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case X86ISD::HADD: return "X86ISD::HADD";
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case X86ISD::HSUB: return "X86ISD::HSUB";
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case X86ISD::FHADD: return "X86ISD::FHADD";
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@ -176,13 +176,11 @@ namespace llvm {
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/// PSIGN - Copy integer sign.
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PSIGN,
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/// BLENDV - Blend where the selector is an XMM.
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/// BLENDV - Blend where the selector is a register.
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BLENDV,
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/// BLENDxx - Blend where the selector is an immediate.
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BLENDPW,
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BLENDPS,
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BLENDPD,
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/// BLENDI - Blend where the selector is an immediate.
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BLENDI,
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/// HADD - Integer horizontal add.
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HADD,
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@ -187,9 +187,7 @@ def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
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def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
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def X86Blendpw : SDNode<"X86ISD::BLENDPW", SDTBlend>;
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def X86Blendps : SDNode<"X86ISD::BLENDPS", SDTBlend>;
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def X86Blendpd : SDNode<"X86ISD::BLENDPD", SDTBlend>;
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def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
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def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
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def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
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def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
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@ -6891,31 +6891,31 @@ let Predicates = [HasAVX] in {
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(v4f64 VR256:$src2))),
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(VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
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def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
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def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
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(imm:$mask))),
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(VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
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(VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
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def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
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(imm:$mask))),
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(VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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(VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
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def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
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def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
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(imm:$mask))),
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(VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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(VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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(imm:$mask))),
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(VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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(VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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(imm:$mask))),
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(VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
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(VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
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(v32i8 VR256:$src2))),
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(VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
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def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
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(VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
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def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
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(imm:$mask))),
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(VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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(VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
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}
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/// SS41I_ternary_int - SSE 4.1 ternary operator
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@ -6979,15 +6979,15 @@ let Predicates = [UseSSE41] in {
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(v2f64 VR128:$src2))),
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(BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
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def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
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def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
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(imm:$mask))),
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(PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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(PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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(imm:$mask))),
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(BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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(BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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(imm:$mask))),
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(BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
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(BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
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}
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@ -7873,6 +7873,13 @@ defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
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VR256, memopv4i64, i256mem>, VEX_L;
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}
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def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
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imm:$mask)),
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(VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
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def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
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imm:$mask)),
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(VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
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//===----------------------------------------------------------------------===//
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// VPBROADCAST - Load from memory and broadcast to all elements of the
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// destination operand
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@ -4,15 +4,62 @@
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; The mask for the vpblendw instruction needs to be identical for both halves
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; of the YMM. Need to use two vpblendw instructions.
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; CHECK: blendw1
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; CHECK: vpblendw
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; CHECK: vpblendw
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; CHECK: vpblendw_test1
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; mask = 10010110,b = 150,d
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; CHECK: vpblendw $150, %ymm
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; CHECK: ret
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define <16 x i16> @blendw1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
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%t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 31>
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define <16 x i16> @vpblendw_test1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
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%t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 23,
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i32 8, i32 25, i32 26, i32 11, i32 28, i32 13, i32 14, i32 31>
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ret <16 x i16> %t
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}
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; CHECK: vpblendw_test2
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; mask1 = 00010110 = 22
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; mask2 = 10000000 = 128
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; CHECK: vpblendw $128, %xmm
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; CHECK: vpblendw $22, %xmm
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; CHECK: vinserti128
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; CHECK: ret
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define <16 x i16> @vpblendw_test2(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
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%t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7,
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i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 31>
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ret <16 x i16> %t
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}
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; CHECK: blend_test1
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; CHECK: vpblendd
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; CHECK: ret
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define <8 x i32> @blend_test1(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
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ret <8 x i32> %t
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}
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; CHECK: blend_test2
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; CHECK: vpblendd
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; CHECK: ret
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define <8 x i32> @blend_test2(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
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ret <8 x i32> %t
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}
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; CHECK: blend_test3
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; CHECK: vblendps
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; CHECK: ret
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define <8 x float> @blend_test3(<8 x float> %a, <8 x float> %b) nounwind alwaysinline {
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%t = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
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ret <8 x float> %t
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}
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; CHECK: blend_test4
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; CHECK: vblendpd
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; CHECK: ret
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define <4 x i64> @blend_test4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
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ret <4 x i64> %t
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}
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; CHECK: vpshufhw $27, %ymm
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define <16 x i16> @vpshufhw(<16 x i16> %src1) nounwind uwtable readnone ssp {
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entry:
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@ -1,4 +1,4 @@
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; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
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; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2
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define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
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entry:
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