From 22ccb1b90501893021c5dea546fd3cad0269c11d Mon Sep 17 00:00:00 2001 From: Ruchira Sasanka Date: Wed, 14 Nov 2001 15:33:58 +0000 Subject: [PATCH] Added interference for args in pseudo instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1300 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 56 ++++++++++++++++++--- lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 56 ++++++++++++++++++--- 2 files changed, 96 insertions(+), 16 deletions(-) diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index db5a50c08c5..e2117bec723 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -263,16 +263,20 @@ void PhyRegAlloc::buildInterferenceGraphs() // iterate over MI operands to find defs for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) { - - if( OpI.isDef() ) { + + if( OpI.isDef() ) { // create a new LR iff this operand is a def addInterference(*OpI, LVSetAI, isCallInst ); - } //if this is a def - } // for all operands + // if there are multiple defs in this instruction e.g. in SETX + // + if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) ) + addInterf4PseudoInstr(MInst); + + // Also add interference for any implicit definitions in a machine // instr (currently, only calls have this). @@ -304,6 +308,46 @@ void PhyRegAlloc::buildInterferenceGraphs() } +//-------------------------------------------------------------------------- +// Pseudo instructions will be exapnded to multiple instructions by the +// assembler. Consequently, all the opernds must get distinct registers +//-------------------------------------------------------------------------- + +void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) { + + // iterate over MI operands to find defs + for( MachineInstr::val_op_const_iterator It1(MInst);!It1.done(); ++It1) { + + const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 ); + + if( !LROfOp1 ) continue; + + MachineInstr::val_op_const_iterator It2 = It1; + ++It2; + + for( ; !It2.done(); ++It2) { + + const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 ); + + if( LROfOp2) { + + RegClass *const RCOfOp1 = LROfOp1->getRegClass(); + RegClass *const RCOfOp2 = LROfOp2->getRegClass(); + + if( RCOfOp1 == RCOfOp2 ){ + RCOfOp1->setInterference( LROfOp1, LROfOp2 ); + //cerr << "\nSet interfs for PSEUDO inst: " << *MInst; + } + + } // if Op2 has a LR + + } // for all other defs in machine instr + + } // for all operands in an instruction + +} + + @@ -1063,10 +1107,6 @@ void PhyRegAlloc::allocateRegisters() // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). - //cout << "\n\n ******** AFTER SCHEDULING **********"; - //MachineCodeForMethod::get(Meth).dump(); - - constructLiveRanges(); // create LR info if( DEBUG_RA ) diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index db5a50c08c5..e2117bec723 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -263,16 +263,20 @@ void PhyRegAlloc::buildInterferenceGraphs() // iterate over MI operands to find defs for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) { - - if( OpI.isDef() ) { + + if( OpI.isDef() ) { // create a new LR iff this operand is a def addInterference(*OpI, LVSetAI, isCallInst ); - } //if this is a def - } // for all operands + // if there are multiple defs in this instruction e.g. in SETX + // + if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) ) + addInterf4PseudoInstr(MInst); + + // Also add interference for any implicit definitions in a machine // instr (currently, only calls have this). @@ -304,6 +308,46 @@ void PhyRegAlloc::buildInterferenceGraphs() } +//-------------------------------------------------------------------------- +// Pseudo instructions will be exapnded to multiple instructions by the +// assembler. Consequently, all the opernds must get distinct registers +//-------------------------------------------------------------------------- + +void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) { + + // iterate over MI operands to find defs + for( MachineInstr::val_op_const_iterator It1(MInst);!It1.done(); ++It1) { + + const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 ); + + if( !LROfOp1 ) continue; + + MachineInstr::val_op_const_iterator It2 = It1; + ++It2; + + for( ; !It2.done(); ++It2) { + + const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 ); + + if( LROfOp2) { + + RegClass *const RCOfOp1 = LROfOp1->getRegClass(); + RegClass *const RCOfOp2 = LROfOp2->getRegClass(); + + if( RCOfOp1 == RCOfOp2 ){ + RCOfOp1->setInterference( LROfOp1, LROfOp2 ); + //cerr << "\nSet interfs for PSEUDO inst: " << *MInst; + } + + } // if Op2 has a LR + + } // for all other defs in machine instr + + } // for all operands in an instruction + +} + + @@ -1063,10 +1107,6 @@ void PhyRegAlloc::allocateRegisters() // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). - //cout << "\n\n ******** AFTER SCHEDULING **********"; - //MachineCodeForMethod::get(Meth).dump(); - - constructLiveRanges(); // create LR info if( DEBUG_RA )