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Add a fast-path for register values. Add support for constant pool entries,

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allowing us to compile this:

float %test2(float* %P) {
        %Q = load float* %P
        %R = add float %Q, 10.1
        ret float %R
}

to this:

_test2:
        lfs r2, 0(r3)
        lis r3, ha16(.CPI_test2_0)
        lfs r3, lo16(.CPI_test2_0)(r3)
        fadds f1, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22962 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-22 01:04:32 +00:00
parent ddf3e7dfd7
commit 23553cfb4a
1 changed files with 13 additions and 1 deletions
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14
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -111,7 +111,16 @@ unsigned SimpleSched::Emit(SDOperand Op) {
// Emit all of the operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
if (Op.getOperand(i).isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
// simpler here.
unsigned R = Emit(Op.getOperand(i));
// Add an operand, unless this corresponds to a chain node.
if (Op.getOperand(i).getValueType() != MVT::Other)
MI->addRegOperand(R, MachineOperand::Use);
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
MI->addZeroExtImm64Operand(C->getValue());
} else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
@ -124,6 +133,9 @@ unsigned SimpleSched::Emit(SDOperand Op) {
} else if (FrameIndexSDNode *FI =
dyn_cast<FrameIndexSDNode>(Op.getOperand(i))) {
MI->addFrameIndexOperand(FI->getIndex());
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(Op.getOperand(i))) {
MI->addConstantPoolIndexOperand(CP->getIndex());
} else {
unsigned R = Emit(Op.getOperand(i));
// Add an operand, unless this corresponds to a chain node.