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[mips][sched] Split IIImul and IIImult into subclasses.
IIImul -> II_MUL IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
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8821f3c6b2
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235a81cbbf
@ -106,9 +106,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM_MM<0, 0x310>;
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def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
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def MULT_MM : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
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def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x22c>;
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def MULTu_MM : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
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def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x26c>;
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def SDIV_MM : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x2ac>;
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@ -178,10 +178,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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MFLO_FM_MM<0x075>;
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/// Multiply Add/Sub Instructions
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def MADD_MM : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>;
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def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>;
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def MSUB_MM : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>;
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def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>;
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def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
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def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
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def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
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def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
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/// Count Leading
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def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
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@ -167,14 +167,14 @@ def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
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}
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
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def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
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def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1d>;
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def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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IIImult>;
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II_DMULT>;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
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IIImult>;
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II_DMULTU>;
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def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>;
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def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
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@ -436,9 +436,9 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
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}
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// Arithmetic Multiply ADD/SUB
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class MArithR<string opstr, bit isComm = 0> :
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class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
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InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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!strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
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!strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
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let Defs = [HI0, LO0];
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let Uses = [HI0, LO0];
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let isCommutable = isComm;
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@ -707,12 +707,13 @@ class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
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// Pseudo multiply add/sub instruction with explicit accumulator register
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// operands.
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class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
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class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
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InstrItinClass itin>
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: PseudoSE<(outs ACC64:$ac),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
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[(set ACC64:$ac,
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(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
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IIImult>,
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itin>,
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PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
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string Constraints = "$acin = $ac";
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}
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@ -929,7 +930,7 @@ def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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ADD_FM<0, 0x23>;
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let Defs = [HI0, LO0] in
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def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
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def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
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ADD_FM<0x1c, 2>;
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def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
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def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
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@ -1069,9 +1070,9 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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}
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/// Multiply and Divide Instructions.
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def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
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def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x18>;
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def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
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def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x19>;
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def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x1a>;
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@ -1104,21 +1105,21 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
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def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
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// MADD*/MSUB*
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def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
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def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
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def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
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def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
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def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
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def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
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def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
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def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
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let Predicates = [HasStdEnc, NotDSP] in {
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def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
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def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
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def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
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def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
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def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
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def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
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def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
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def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
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def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
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def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
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def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
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def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
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def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
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def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
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def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
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}
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def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
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@ -20,8 +20,6 @@ def IIAlu : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIBranch : InstrItinClass;
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def IIImul : InstrItinClass;
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def IIImult : InstrItinClass;
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def IIIdiv : InstrItinClass;
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def IIslt : InstrItinClass;
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def IIFcvt : InstrItinClass;
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@ -49,6 +47,8 @@ def II_CLO : InstrItinClass;
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def II_CLZ : InstrItinClass;
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def II_DADDIU : InstrItinClass;
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def II_DADDU : InstrItinClass;
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def II_DMULT : InstrItinClass;
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def II_DMULTU : InstrItinClass;
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def II_DROTR : InstrItinClass;
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def II_DROTR32 : InstrItinClass;
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def II_DROTRV : InstrItinClass;
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@ -63,12 +63,19 @@ def II_DSRL32 : InstrItinClass;
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def II_DSRLV : InstrItinClass;
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def II_DSUBU : InstrItinClass;
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def II_LUI : InstrItinClass;
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def II_MADD : InstrItinClass;
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def II_MADDU : InstrItinClass;
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def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
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def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
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def II_MOVF : InstrItinClass;
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def II_MOVN : InstrItinClass;
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def II_MOVT : InstrItinClass;
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def II_MOVZ : InstrItinClass;
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def II_MUL : InstrItinClass;
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def II_MULT : InstrItinClass;
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def II_MULTU : InstrItinClass;
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def II_MSUB : InstrItinClass;
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def II_MSUBU : InstrItinClass;
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def II_NOR : InstrItinClass;
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def II_OR : InstrItinClass;
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def II_ORI : InstrItinClass;
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@ -133,10 +140,17 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
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InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
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InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<IIImult , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
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InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
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