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[mips][microMIPS] Implement JR16 instruction
Differential Revision: http://reviews.llvm.org/D5062 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219498 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -117,6 +117,15 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
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let Defs = [RA];
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}
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// 16-bit Jump Reg
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class JumpRegMM16<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
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[], IIBranch, FrmR> {
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let hasDelaySlot = 1;
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let isBranch = 1;
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let isIndirectBranch = 1;
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}
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// Base class for JRADDIUSP instruction.
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class JumpRAddiuStackMM16 :
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MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
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@ -173,6 +182,7 @@ def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
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def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
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def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
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def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
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def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
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class WaitMM<string opstr> :
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InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
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@ -19,6 +19,8 @@
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# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK-EL: jalrs16 $9 # encoding: [0xe9,0x45]
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# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c]
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# CHECK-EL: jr16 $9 # encoding: [0x89,0x45]
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# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
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#------------------------------------------------------------------------------
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# Big endian
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#------------------------------------------------------------------------------
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@ -32,6 +34,8 @@
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# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK-EB: jalrs16 $9 # encoding: [0x45,0xe9]
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# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00]
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# CHECK-EB: jr16 $9 # encoding: [0x45,0x89]
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# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
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addius5 $7, -2
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mfhi $9
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@ -41,3 +45,4 @@
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jalr $9
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jraddiusp 20
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jalrs16 $9
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jr16 $9
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