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Pass the value type to TLI::getRegisterByName

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We must validate the value type in TLI::getRegisterByName, because if we
don't and the wrong type was used with the IR intrinsic, then we'll assert
(because we won't be able to find a valid register class with which to
construct the requested copy operation). For PPC64, additionally, the type
information is necessary to decide between the 64-bit register and the 32-bit
subregister.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-05-11 19:29:07 +00:00
parent 94a03fcf38
commit 24f554f052
10 changed files with 15 additions and 11 deletions
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2
include/llvm/Target/TargetLowering.h
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@ -2217,7 +2217,7 @@ public:
/// Return the register ID of the name passed in. Used by named register
/// global variables extension. There is no target-independent behaviour
/// so the default action is to bail.
virtual unsigned getRegisterByName(const char* RegName) const {
virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
report_fatal_error("Named registers not implemented for this target");
}

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -1813,7 +1813,7 @@ SDNode
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
unsigned Reg = getTargetLowering()->getRegisterByName(
RegStr->getString().data());
RegStr->getString().data(), Op->getValueType(0));
SDValue New = CurDAG->getCopyFromReg(
CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
New->setNodeId(-1);
@ -1826,7 +1826,7 @@ SDNode
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
unsigned Reg = getTargetLowering()->getRegisterByName(
RegStr->getString().data());
RegStr->getString().data(), Op->getOperand(2).getValueType());
SDValue New = CurDAG->getCopyToReg(
CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
New->setNodeId(-1);

3
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2409,7 +2409,8 @@ SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
unsigned AArch64TargetLowering::getRegisterByName(const char* RegName) const {
unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
EVT VT) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("sp", AArch64::XSP)
.Default(0);

2
lib/Target/AArch64/AArch64ISelLowering.h
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@ -350,7 +350,7 @@ public:
SDValue PerformDAGCombine(SDNode *N,DAGCombinerInfo &DCI) const override;
unsigned getRegisterByName(const char* RegName) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be

3
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -3925,7 +3925,8 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
unsigned ARMTargetLowering::getRegisterByName(const char* RegName) const {
unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
EVT VT) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("sp", ARM::SP)
.Default(0);

2
lib/Target/ARM/ARMISelLowering.h
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@ -471,7 +471,7 @@ namespace llvm {
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
unsigned getRegisterByName(const char* RegName) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be

3
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -3445,7 +3445,8 @@ SDValue ARM64TargetLowering::LowerFRAMEADDR(SDValue Op,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
unsigned ARM64TargetLowering::getRegisterByName(const char* RegName) const {
unsigned ARM64TargetLowering::getRegisterByName(const char* RegName,
EVT VT) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("sp", ARM64::SP)
.Default(0);

2
lib/Target/ARM64/ARM64ISelLowering.h
View File

@ -411,7 +411,7 @@ private:
ConstraintType
getConstraintType(const std::string &Constraint) const override;
unsigned getRegisterByName(const char* RegName) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.

3
lib/Target/X86/X86ISelLowering.cpp
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@ -12817,7 +12817,8 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
unsigned X86TargetLowering::getRegisterByName(const char* RegName) const {
unsigned X86TargetLowering::getRegisterByName(const char* RegName,
EVT VT) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("esp", X86::ESP)
.Case("rsp", X86::RSP)

2
lib/Target/X86/X86ISelLowering.h
View File

@ -786,7 +786,7 @@ namespace llvm {
return nullptr; // nothing to do, move along.
}
unsigned getRegisterByName(const char* RegName) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.