RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-01-26 14:25:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

AMDGPU: Set isAllocatable = 0 on VS_32/VS_64

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252674 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-11-11 00:01:32 +00:00
parent 662c69d8c2
commit 259b76dfea
5 changed files with 9 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -79,8 +79,6 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
STI.getMaxWavesPerCU());
unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
unsigned VSLimit = SGPRLimit + VGPRLimit;
for (regclass_iterator I = regclass_begin(), E = regclass_end();
I != E; ++I) {
const TargetRegisterClass *RC = *I;
@ -88,11 +86,7 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
unsigned NumSubRegs = std::max((int)RC->getSize() / 4, 1);
unsigned Limit;
if (isPseudoRegClass(RC)) {
// FIXME: This is a hack. We should never be considering the pressure of
// these since no virtual register should ever have this class.
Limit = VSLimit;
} else if (isSGPRClass(RC)) {
if (isSGPRClass(RC)) {
Limit = SGPRLimit / NumSubRegs;
} else {
Limit = VGPRLimit / NumSubRegs;

7
lib/Target/AMDGPU/SIRegisterInfo.h
View File

@ -59,13 +59,6 @@ public:
/// \returns true if this class contains VGPR registers.
bool hasVGPRs(const TargetRegisterClass *RC) const;
/// returns true if this is a pseudoregister class combination of VGPRs and
/// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on
/// them.
static bool isPseudoRegClass(const TargetRegisterClass *RC) {
return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
}
/// \returns A VGPR reg class with the same width as \p SRC
const TargetRegisterClass *getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const;

7
lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -272,9 +272,12 @@ def SCSrc_32 : RegInlineOperand<SReg_32> {
// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
//===----------------------------------------------------------------------===//
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32, VGPR_32)> {
let isAllocatable = 0;
}
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add SReg_64, VReg_64)> {
let isAllocatable = 0;
let CopyCost = 2;
}

4
test/CodeGen/AMDGPU/ftrunc.f64.ll
View File

@ -27,8 +27,8 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
; SI: s_lshr_b64
; SI: s_not_b64
; SI: s_and_b64
; SI-DAG: s_not_b64
; SI-DAG: s_and_b64
; SI-DAG: cmp_gt_i32
; SI-DAG: cndmask_b32
; SI-DAG: cndmask_b32

2
test/CodeGen/AMDGPU/llvm.round.f64.ll
View File

@ -21,7 +21,7 @@ define void @round_f64(double addrspace(1)* %out, double %x) #0 {
; SI-DAG: v_cmp_eq_i32
; SI-DAG: s_mov_b32 [[BFIMASK:s[0-9]+]], 0x7fffffff
; SI-DAG: v_cmp_gt_i32_e32
; SI-DAG: v_cmp_gt_i32
; SI-DAG: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[BFIMASK]]
; SI: buffer_store_dwordx2