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R600: Some factorization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
dcfcf1d1ff
commit
25c209e9a2
@ -172,22 +172,20 @@ private:
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AMDGPU::ALU_LITERAL_Z,
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AMDGPU::ALU_LITERAL_W
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};
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for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3 > Srcs =
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TII->getSrcs(MI);
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for (unsigned i = 0, e = Srcs.size(); i < e; ++i) {
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if (Srcs[i].first->getReg() != AMDGPU::ALU_LITERAL_X)
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continue;
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if (MO.getReg() != AMDGPU::ALU_LITERAL_X)
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continue;
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unsigned ImmIdx = TII->getOperandIdx(MI->getOpcode(), R600Operands::IMM);
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int64_t Imm = MI->getOperand(ImmIdx).getImm();
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int64_t Imm = Srcs[i].second;
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std::vector<int64_t>::iterator It =
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std::find(Lits.begin(), Lits.end(), Imm);
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if (It != Lits.end()) {
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unsigned Index = It - Lits.begin();
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MO.setReg(LiteralRegs[Index]);
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Srcs[i].first->setReg(LiteralRegs[Index]);
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} else {
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assert(Lits.size() < 4 && "Too many literals in Instruction Group");
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MO.setReg(LiteralRegs[Lits.size()]);
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Srcs[i].first->setReg(LiteralRegs[Lits.size()]);
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Lits.push_back(Imm);
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}
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}
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@ -89,31 +89,6 @@ private:
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}
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}
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// Register Idx, then Const value
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std::vector<std::pair<unsigned, unsigned> > ExtractConstRead(MachineInstr *MI)
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const {
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const R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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std::vector<std::pair<unsigned, unsigned> > Result;
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if (!TII->isALUInstr(MI->getOpcode()))
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return Result;
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[j][0]);
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if (SrcIdx < 0)
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break;
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if (MI->getOperand(SrcIdx).getReg() == AMDGPU::ALU_CONST) {
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unsigned Const = MI->getOperand(
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TII->getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
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Result.push_back(std::pair<unsigned, unsigned>(SrcIdx, Const));
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}
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}
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return Result;
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}
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std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
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// Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
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// (See also R600ISelLowering.cpp)
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@ -131,9 +106,12 @@ private:
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bool SubstituteKCacheBank(MachineInstr *MI,
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std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
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std::vector<std::pair<unsigned, unsigned> > UsedKCache;
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std::vector<std::pair<unsigned, unsigned> > Consts = ExtractConstRead(MI);
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Consts =
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TII->getSrcs(MI);
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assert(TII->isALUInstr(MI->getOpcode()) && "Can't assign Const");
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
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continue;
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unsigned Sel = Consts[i].second;
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unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
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unsigned KCacheIndex = Index * 4 + Chan;
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@ -159,19 +137,22 @@ private:
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return false;
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}
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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switch(UsedKCache[i].first) {
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for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
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if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
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continue;
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switch(UsedKCache[j].first) {
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case 0:
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MI->getOperand(Consts[i].first).setReg(
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AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[i].second));
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Consts[i].first->setReg(
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AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
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break;
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case 1:
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MI->getOperand(Consts[i].first).setReg(
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AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[i].second));
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Consts[i].first->setReg(
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AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
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break;
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default:
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llvm_unreachable("Wrong Cache Line");
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}
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j++;
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}
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return true;
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}
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@ -168,6 +168,156 @@ bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
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usesTextureCache(MI->getOpcode());
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}
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SmallVector<std::pair<MachineOperand *, int64_t>, 3>
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R600InstrInfo::getSrcs(MachineInstr *MI) const {
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SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
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static const R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
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if (SrcIdx < 0)
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break;
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MachineOperand &MO = MI->getOperand(SrcIdx);
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unsigned Reg = MI->getOperand(SrcIdx).getReg();
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if (Reg == AMDGPU::ALU_CONST) {
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unsigned Sel = MI->getOperand(
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getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
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continue;
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}
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if (Reg == AMDGPU::ALU_LITERAL_X) {
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unsigned Imm = MI->getOperand(
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getOperandIdx(MI->getOpcode(), R600Operands::IMM)).getImm();
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
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continue;
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}
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
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}
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return Result;
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}
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std::vector<std::pair<int, unsigned> >
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R600InstrInfo::ExtractSrcs(MachineInstr *MI,
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const DenseMap<unsigned, unsigned> &PV)
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const {
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
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const std::pair<int, unsigned> DummyPair(-1, 0);
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std::vector<std::pair<int, unsigned> > Result;
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unsigned i = 0;
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for (unsigned n = Srcs.size(); i < n; ++i) {
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unsigned Reg = Srcs[i].first->getReg();
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unsigned Index = RI.getEncodingValue(Reg) & 0xff;
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unsigned Chan = RI.getHWRegChan(Reg);
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if (Index > 127) {
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Result.push_back(DummyPair);
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continue;
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}
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if (PV.find(Index) != PV.end()) {
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Result.push_back(DummyPair);
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continue;
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}
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Result.push_back(std::pair<int, unsigned>(Index, Chan));
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}
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for (; i < 3; ++i)
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Result.push_back(DummyPair);
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return Result;
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}
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static std::vector<std::pair<int, unsigned> >
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Swizzle(std::vector<std::pair<int, unsigned> > Src,
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R600InstrInfo::BankSwizzle Swz) {
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switch (Swz) {
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case R600InstrInfo::ALU_VEC_012:
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break;
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case R600InstrInfo::ALU_VEC_021:
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std::swap(Src[1], Src[2]);
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break;
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case R600InstrInfo::ALU_VEC_102:
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std::swap(Src[0], Src[1]);
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break;
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case R600InstrInfo::ALU_VEC_120:
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std::swap(Src[0], Src[1]);
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std::swap(Src[0], Src[2]);
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break;
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case R600InstrInfo::ALU_VEC_201:
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std::swap(Src[0], Src[2]);
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std::swap(Src[0], Src[1]);
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break;
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case R600InstrInfo::ALU_VEC_210:
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std::swap(Src[0], Src[2]);
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break;
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}
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return Src;
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}
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static bool
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isLegal(const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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unsigned CheckedSize) {
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int Vector[4][3];
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memset(Vector, -1, sizeof(Vector));
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for (unsigned i = 0; i < CheckedSize; i++) {
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const std::vector<std::pair<int, unsigned> > &Srcs =
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Swizzle(IGSrcs[i], Swz[i]);
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for (unsigned j = 0; j < 3; j++) {
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const std::pair<int, unsigned> &Src = Srcs[j];
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if (Src.first < 0)
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continue;
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if (Vector[Src.second][j] < 0)
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Vector[Src.second][j] = Src.first;
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if (Vector[Src.second][j] != Src.first)
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return false;
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}
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}
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return true;
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}
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static bool recursiveFitsFPLimitation(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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unsigned Depth = 0) {
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if (!isLegal(IGSrcs, SwzCandidate, Depth))
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return false;
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if (IGSrcs.size() == Depth)
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return true;
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unsigned i = SwzCandidate[Depth];
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for (; i < 6; i++) {
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SwzCandidate[Depth] = (R600InstrInfo::BankSwizzle) i;
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if (recursiveFitsFPLimitation(IGSrcs, SwzCandidate, Depth + 1))
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return true;
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}
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SwzCandidate[Depth] = R600InstrInfo::ALU_VEC_012;
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return false;
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}
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bool
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R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<BankSwizzle> &ValidSwizzle)
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const {
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//Todo : support shared src0 - src1 operand
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std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
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ValidSwizzle.clear();
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for (unsigned i = 0, e = IG.size(); i < e; ++i) {
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IGSrcs.push_back(ExtractSrcs(IG[i], PV));
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unsigned Op = getOperandIdx(IG[i]->getOpcode(),
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R600Operands::BANK_SWIZZLE);
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ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
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IG[i]->getOperand(Op).getImm());
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}
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bool Result = recursiveFitsFPLimitation(IGSrcs, ValidSwizzle);
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if (!Result)
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return false;
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return true;
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}
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bool
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R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
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const {
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@ -197,34 +347,22 @@ bool
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R600InstrInfo::canBundle(const std::vector<MachineInstr *> &MIs) const {
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std::vector<unsigned> Consts;
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for (unsigned i = 0, n = MIs.size(); i < n; i++) {
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const MachineInstr *MI = MIs[i];
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const R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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MachineInstr *MI = MIs[i];
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if (!isALUInstr(MI->getOpcode()))
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continue;
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
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if (SrcIdx < 0)
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break;
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unsigned Reg = MI->getOperand(SrcIdx).getReg();
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if (Reg == AMDGPU::ALU_CONST) {
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unsigned Const = MI->getOperand(
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getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
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Consts.push_back(Const);
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continue;
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}
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if (AMDGPU::R600_KC0RegClass.contains(Reg) ||
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AMDGPU::R600_KC1RegClass.contains(Reg)) {
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unsigned Index = RI.getEncodingValue(Reg) & 0xff;
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unsigned Chan = RI.getHWRegChan(Reg);
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Srcs =
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getSrcs(MI);
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for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
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std::pair<MachineOperand *, unsigned> Src = Srcs[j];
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if (Src.first->getReg() == AMDGPU::ALU_CONST)
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Consts.push_back(Src.second);
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if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
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AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
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unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
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unsigned Chan = RI.getHWRegChan(Src.first->getReg());
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Consts.push_back((Index << 2) | Chan);
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continue;
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}
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}
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}
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@ -36,8 +36,19 @@ namespace llvm {
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const AMDGPUSubtarget &ST;
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int getBranchInstr(const MachineOperand &op) const;
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std::vector<std::pair<int, unsigned> >
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ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV) const;
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public:
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enum BankSwizzle {
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ALU_VEC_012 = 0,
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ALU_VEC_021,
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ALU_VEC_120,
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ALU_VEC_102,
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ALU_VEC_201,
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ALU_VEC_210
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};
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explicit R600InstrInfo(AMDGPUTargetMachine &tm);
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const R600RegisterInfo &getRegisterInfo() const;
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@ -62,6 +73,23 @@ namespace llvm {
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bool usesTextureCache(unsigned Opcode) const;
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bool usesTextureCache(const MachineInstr *MI) const;
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/// \returns a pair for each src of an ALU instructions.
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/// The first member of a pair is the register id.
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/// If register is ALU_CONST, second member is SEL.
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/// If register is ALU_LITERAL, second member is IMM.
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/// Otherwise, second member value is undefined.
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SmallVector<std::pair<MachineOperand *, int64_t>, 3>
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getSrcs(MachineInstr *MI) const;
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/// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
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/// returns true and the first (in lexical order) BankSwizzle affectation
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/// starting from the one already provided in the Instruction Group MIs that
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/// fits Read Port limitations in BS if available. Otherwise returns false
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/// and undefined content in BS.
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/// PV holds GPR to PV registers in the Instruction Group MIs.
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bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<BankSwizzle> &BS) const;
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bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
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bool canBundle(const std::vector<MachineInstr *> &) const;
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@ -60,15 +60,6 @@ private:
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const R600InstrInfo *TII;
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const R600RegisterInfo &TRI;
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enum BankSwizzle {
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ALU_VEC_012 = 0,
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ALU_VEC_021,
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ALU_VEC_120,
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ALU_VEC_102,
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ALU_VEC_201,
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ALU_VEC_210
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};
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unsigned getSlot(const MachineInstr *MI) const {
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return TRI.getHWRegChan(MI->getOperand(0).getReg());
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}
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@ -222,7 +213,9 @@ public:
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});
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const DenseMap<unsigned, unsigned> &PV =
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getPreviousVector(CurrentPacketMIs.front());
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bool FitsReadPortLimits = fitsReadPortLimitation(CurrentPacketMIs, PV);
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std::vector<R600InstrInfo::BankSwizzle> BS;
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bool FitsReadPortLimits =
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TII->fitsReadPortLimitations(CurrentPacketMIs, PV, BS);
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DEBUG(
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if (!FitsReadPortLimits) {
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dbgs() << "Couldn't pack :\n";
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@ -235,6 +228,14 @@ public:
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dbgs() << "because of Read port limitations\n";
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});
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bool isBundlable = FitsConstLimits && FitsReadPortLimits;
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if (isBundlable) {
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for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
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MachineInstr *MI = CurrentPacketMIs[i];
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unsigned Op = TII->getOperandIdx(MI->getOpcode(),
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R600Operands::BANK_SWIZZLE);
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MI->getOperand(Op).setImm(BS[i]);
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}
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}
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CurrentPacketMIs.pop_back();
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if (!isBundlable) {
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endPacket(MI->getParent(), MI);
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@ -246,134 +247,6 @@ public:
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substitutePV(MI, PV);
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return VLIWPacketizerList::addToPacket(MI);
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}
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private:
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std::vector<std::pair<int, unsigned> >
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ExtractSrcs(const MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV)
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const {
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R600Operands::Ops Ops[] = {
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R600Operands::SRC0,
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R600Operands::SRC1,
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R600Operands::SRC2
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};
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std::vector<std::pair<int, unsigned> > Result;
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for (unsigned i = 0; i < 3; i++) {
|
||||
int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
|
||||
if (OperandIdx < 0){
|
||||
Result.push_back(std::pair<int, unsigned>(-1,0));
|
||||
continue;
|
||||
}
|
||||
unsigned Src = MI->getOperand(OperandIdx).getReg();
|
||||
if (PV.find(Src) != PV.end()) {
|
||||
Result.push_back(std::pair<int, unsigned>(-1,0));
|
||||
continue;
|
||||
}
|
||||
unsigned Reg = TRI.getEncodingValue(Src) & 0xff;
|
||||
if (Reg > 127) {
|
||||
Result.push_back(std::pair<int, unsigned>(-1,0));
|
||||
continue;
|
||||
}
|
||||
unsigned Chan = TRI.getHWRegChan(Src);
|
||||
Result.push_back(std::pair<int, unsigned>(Reg, Chan));
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
std::vector<std::pair<int, unsigned> >
|
||||
Swizzle(std::vector<std::pair<int, unsigned> > Src,
|
||||
BankSwizzle Swz) const {
|
||||
switch (Swz) {
|
||||
case ALU_VEC_012:
|
||||
break;
|
||||
case ALU_VEC_021:
|
||||
std::swap(Src[1], Src[2]);
|
||||
break;
|
||||
case ALU_VEC_102:
|
||||
std::swap(Src[0], Src[1]);
|
||||
break;
|
||||
case ALU_VEC_120:
|
||||
std::swap(Src[0], Src[1]);
|
||||
std::swap(Src[0], Src[2]);
|
||||
break;
|
||||
case ALU_VEC_201:
|
||||
std::swap(Src[0], Src[2]);
|
||||
std::swap(Src[0], Src[1]);
|
||||
break;
|
||||
case ALU_VEC_210:
|
||||
std::swap(Src[0], Src[2]);
|
||||
break;
|
||||
}
|
||||
return Src;
|
||||
}
|
||||
|
||||
bool isLegal(const std::vector<MachineInstr *> &IG,
|
||||
const std::vector<BankSwizzle> &Swz,
|
||||
const DenseMap<unsigned, unsigned> &PV) const {
|
||||
assert (Swz.size() == IG.size());
|
||||
int Vector[4][3];
|
||||
memset(Vector, -1, sizeof(Vector));
|
||||
for (unsigned i = 0, e = IG.size(); i < e; i++) {
|
||||
const std::vector<std::pair<int, unsigned> > &Srcs =
|
||||
Swizzle(ExtractSrcs(IG[i], PV), Swz[i]);
|
||||
for (unsigned j = 0; j < 3; j++) {
|
||||
const std::pair<int, unsigned> &Src = Srcs[j];
|
||||
if (Src.first < 0)
|
||||
continue;
|
||||
if (Vector[Src.second][j] < 0)
|
||||
Vector[Src.second][j] = Src.first;
|
||||
if (Vector[Src.second][j] != Src.first)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool recursiveFitsFPLimitation(
|
||||
std::vector<MachineInstr *> IG,
|
||||
const DenseMap<unsigned, unsigned> &PV,
|
||||
std::vector<BankSwizzle> &SwzCandidate,
|
||||
std::vector<MachineInstr *> CurrentlyChecked)
|
||||
const {
|
||||
if (!isLegal(CurrentlyChecked, SwzCandidate, PV))
|
||||
return false;
|
||||
if (IG.size() == CurrentlyChecked.size()) {
|
||||
return true;
|
||||
}
|
||||
BankSwizzle AvailableSwizzle[] = {
|
||||
ALU_VEC_012,
|
||||
ALU_VEC_021,
|
||||
ALU_VEC_120,
|
||||
ALU_VEC_102,
|
||||
ALU_VEC_201,
|
||||
ALU_VEC_210
|
||||
};
|
||||
CurrentlyChecked.push_back(IG[CurrentlyChecked.size()]);
|
||||
for (unsigned i = 0; i < 6; i++) {
|
||||
SwzCandidate.push_back(AvailableSwizzle[i]);
|
||||
if (recursiveFitsFPLimitation(IG, PV, SwzCandidate, CurrentlyChecked))
|
||||
return true;
|
||||
SwzCandidate.pop_back();
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool fitsReadPortLimitation(
|
||||
std::vector<MachineInstr *> IG,
|
||||
const DenseMap<unsigned, unsigned> &PV)
|
||||
const {
|
||||
//Todo : support shared src0 - src1 operand
|
||||
std::vector<BankSwizzle> SwzCandidate;
|
||||
bool Result = recursiveFitsFPLimitation(IG, PV, SwzCandidate,
|
||||
std::vector<MachineInstr *>());
|
||||
if (!Result)
|
||||
return false;
|
||||
for (unsigned i = 0, e = IG.size(); i < e; i++) {
|
||||
MachineInstr *MI = IG[i];
|
||||
unsigned Op = TII->getOperandIdx(MI->getOpcode(),
|
||||
R600Operands::BANK_SWIZZLE);
|
||||
MI->getOperand(Op).setImm(SwzCandidate[i]);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user