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[AArch64] Adjust the scheduling model for Exynos M1.

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Further refine the model for loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evandro Menezes 2016-09-06 19:22:19 +00:00
parent ec44cfdaf0
commit 25c97c0417
1 changed files with 11 additions and 11 deletions
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22
lib/Target/AArch64/AArch64SchedM1.td
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@ -64,9 +64,16 @@ let SchedModel = ExynosM1Model in {
//===----------------------------------------------------------------------===//
// Coarse scheduling model for the Exynos-M1.
def M1WriteLDIdxA : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
def M1WriteLDIdxB : SchedWriteRes<[M1UnitL,
M1UnitALU]> { let Latency = 5; }
def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
def M1WriteLA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteL5]>]>;
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
// Branch instructions.
// NOTE: Unconditional direct branches actually take neither cycles nor units.
@ -106,14 +113,7 @@ def : WriteRes<WriteAdr, []> { let Latency = 0; }
// Load instructions.
def : WriteRes<WriteLD, [M1UnitL]> { let Latency = 4; }
def : WriteRes<WriteLDHi, [M1UnitALU]> { let Latency = 4; }
def M1WriteLDIdx : SchedWriteVariant<[
SchedVar<ScaledIdxPred, [M1WriteLDIdxB]>,
SchedVar<NoSchedPred, [M1WriteLDIdxA]>]>;
def : SchedAlias<WriteLDIdx, M1WriteLDIdx>;
def M1ReadAdrBase : SchedReadVariant<[
SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
def : SchedAlias<WriteLDIdx, M1WriteLA>;
// Store instructions.
def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }