diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td
index 52d45ad9bd9..9874feccb3f 100644
--- a/lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -751,7 +751,7 @@ class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
   let Inst{3-0}   = 0b0000;
 }
 
-class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
   bits<3> rt;
   bits<3> rs;
 
diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 4286c36e21c..69bdfa0d4b2 100644
--- a/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -830,7 +830,7 @@ class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-      MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+      MMR6Arch<"sdbbp16">;
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
diff --git a/test/CodeGen/Mips/micromips-or16.ll b/test/CodeGen/Mips/micromips-or16.ll
index 82ea9c687df..ae2c53884ef 100644
--- a/test/CodeGen/Mips/micromips-or16.ll
+++ b/test/CodeGen/Mips/micromips-or16.ll
@@ -1,18 +1,23 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -asm-show-inst < %s | FileCheck %s
 
-define i32 @main() {
-entry:
-  %retval = alloca i32, align 4
-  %a = alloca i32, align 4
-  %b = alloca i32, align 4
-  %c = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32, i32* %b, align 4
-  %1 = load i32, i32* %c, align 4
-  %or = or i32 %0, %1
-  store i32 %or, i32* %a, align 4
-  ret i32 0
+; Branch instruction added to enable FastISel::selectOperator
+; to select OR instruction
+define i32 @f1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: f1
+; CHECK-NOT: OR16_MMR6
+      %1 = or i32 %a, %b
+       br label %b1
+b1:
+       ret i32 %1
 }
 
+define i32 @f2(i32 signext %a, i32 signext %b) {
+entry:
+; CHECK-LABEL: f2
 ; CHECK: or16
+  %0 = or i32 %a, %b
+  ret i32 %0
+}