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[X86][SSE] Simplify float domain requirement in unary shuffle matching.

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The AVX1-only limit is never actually required in matchUnaryVectorShuffle

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291244 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2017-01-06 17:00:59 +00:00
parent 943d501146
commit 2634e452b0
1 changed files with 1 additions and 2 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -25961,8 +25961,7 @@ static bool matchUnaryVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
unsigned &Shuffle, MVT &SrcVT, MVT &DstVT) {
unsigned NumMaskElts = Mask.size();
unsigned MaskEltSize = MaskVT.getScalarSizeInBits();
bool FloatDomain = MaskVT.isFloatingPoint() ||
(!Subtarget.hasAVX2() && MaskVT.is256BitVector());
bool FloatDomain = MaskVT.isFloatingPoint();
// Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits (MOVSS).
if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2())) &&