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Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
ade7d00f5a
commit
26d2f0ac91
@ -189,6 +189,7 @@ def MSRMaskOperand : AsmOperandClass {
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}
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def msr_mask : Operand<i32> {
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let PrintMethod = "printMSRMaskOperand";
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let DecoderMethod = "DecodeMSRMask";
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let ParserMatchClass = MSRMaskOperand;
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}
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@ -1259,6 +1259,37 @@ multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
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}
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}
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
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InstrItinClass iir, PatFrag opnode> {
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// Note: We use the complex addrmode_imm12 rather than just an input
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// GPR and a constrained immediate so that we can use this to match
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// frame index references and avoid matching constant pool references.
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def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
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AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
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[(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
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bits<4> Rt;
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bits<17> addr;
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
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AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
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[(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
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bits<4> Rt;
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bits<17> shift;
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let shift{4} = 0; // Inst{4} = 0
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let Inst{23} = shift{12}; // U (add = ('U' == 1))
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let Inst{19-16} = shift{16-13}; // Rn
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let Inst{15-12} = Rt;
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let Inst{11-0} = shift{11-0};
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}
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}
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}
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multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
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InstrItinClass iir, PatFrag opnode> {
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// Note: We use the complex addrmode_imm12 rather than just an input
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@ -1287,6 +1318,37 @@ multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
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let Inst{11-0} = shift{11-0};
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}
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}
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multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
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InstrItinClass iir, PatFrag opnode> {
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// Note: We use the complex addrmode_imm12 rather than just an input
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// GPR and a constrained immediate so that we can use this to match
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// frame index references and avoid matching constant pool references.
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def i12 : AI2ldst<0b010, 0, isByte, (outs),
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(ins GPRnopc:$Rt, addrmode_imm12:$addr),
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AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
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[(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
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bits<4> Rt;
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bits<17> addr;
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
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AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
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[(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
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bits<4> Rt;
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bits<17> shift;
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let shift{4} = 0; // Inst{4} = 0
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let Inst{23} = shift{12}; // U (add = ('U' == 1))
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let Inst{19-16} = shift{16-13}; // Rn
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let Inst{15-12} = Rt;
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let Inst{11-0} = shift{11-0};
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}
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -1894,11 +1956,11 @@ def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
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defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
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UnOpFrag<(load node:$Src)>>;
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defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
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defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi8 node:$Src)>>;
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defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
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BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
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defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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// Special LDR for loads from non-pc-relative constpools.
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@ -133,6 +133,8 @@ static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
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@ -759,6 +761,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
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static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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// Empty register lists are not allowed.
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if (CountPopulation_32(Val) == 0) return false;
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for (unsigned i = 0; i < 16; ++i) {
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if (Val & (1 << i)) {
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if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
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@ -2467,3 +2471,9 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
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return true;
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}
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static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (!Val) return false;
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Inst.addOperand(MCOperand::CreateImm(Val));
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return true;
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}
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@ -1,8 +1,7 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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@ -1,11 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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#
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# if BitCount(registers) < 1 then UNPREDICTABLE
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0x00 0xc7
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@ -1,11 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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#
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# if t == 15 then UNPREDICTABLE
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0x00 0xf0 0xcf 0xe7
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