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https://github.com/RPCSX/llvm.git
synced 2024-12-05 02:16:46 +00:00
Eliminate more special cases for opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
f6b23bfc79
commit
26ea8f982f
@ -780,8 +780,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::MERGE_VALUES:
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case ISD::EH_RETURN:
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case ISD::FRAME_TO_ARGS_OFFSET:
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case ISD::EXCEPTIONADDR:
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case ISD::EHSELECTION:
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// These operations lie about being legal: when they claim to be legal,
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// they should actually be expanded.
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Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
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@ -885,74 +883,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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#endif
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assert(0 && "Do not know how to legalize this operator!");
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abort();
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case ISD::EXCEPTIONADDR: {
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Tmp1 = LegalizeOp(Node->getOperand(0));
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MVT VT = Node->getValueType(0);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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unsigned Reg = TLI.getExceptionAddressRegister();
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Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
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}
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break;
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Op, DAG);
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if (Result.getNode()) break;
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// Fall Thru
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case TargetLowering::Legal: {
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SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
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Result = DAG.getMergeValues(Ops, 2, dl);
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break;
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}
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}
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}
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if (Result.getNode()->getNumValues() == 1) break;
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assert(Result.getNode()->getNumValues() == 2 &&
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"Cannot return more than two values!");
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// Since we produced two values, make sure to remember that we
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// legalized both of them.
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Tmp1 = LegalizeOp(Result);
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Tmp2 = LegalizeOp(Result.getValue(1));
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AddLegalizedOperand(Op.getValue(0), Tmp1);
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AddLegalizedOperand(Op.getValue(1), Tmp2);
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return Op.getResNo() ? Tmp2 : Tmp1;
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case ISD::EHSELECTION: {
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Tmp1 = LegalizeOp(Node->getOperand(0));
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Tmp2 = LegalizeOp(Node->getOperand(1));
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MVT VT = Node->getValueType(0);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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unsigned Reg = TLI.getExceptionSelectorRegister();
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Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
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}
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break;
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Op, DAG);
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if (Result.getNode()) break;
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// Fall Thru
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case TargetLowering::Legal: {
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SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
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Result = DAG.getMergeValues(Ops, 2, dl);
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break;
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}
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}
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}
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if (Result.getNode()->getNumValues() == 1) break;
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assert(Result.getNode()->getNumValues() == 2 &&
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"Cannot return more than two values!");
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// Since we produced two values, make sure to remember that we
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// legalized both of them.
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Tmp1 = LegalizeOp(Result);
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Tmp2 = LegalizeOp(Result.getValue(1));
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AddLegalizedOperand(Op.getValue(0), Tmp1);
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AddLegalizedOperand(Op.getValue(1), Tmp2);
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return Op.getResNo() ? Tmp2 : Tmp1;
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case ISD::DBG_STOPPOINT:
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assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
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@ -2055,128 +1985,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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// Binary operators
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case ISD::SUB:
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case ISD::MUL:
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case ISD::MULHS:
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case ISD::MULHU:
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case ISD::UDIV:
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case ISD::SDIV:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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default: assert(0 && "BinOp legalize operation not supported");
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case TargetLowering::Legal: break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.getNode()) {
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Result = Tmp1;
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break;
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}
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// Fall through if the custom lower can't deal with the operation
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case TargetLowering::Expand: {
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MVT VT = Op.getValueType();
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// See if multiply or divide can be lowered using two-result operations.
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (Node->getOpcode() == ISD::MUL) {
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// We just need the low half of the multiply; try both the signed
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// and unsigned forms. If the target supports both SMUL_LOHI and
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// UMUL_LOHI, form a preference by checking which forms of plain
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// MULH it supports.
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bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
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bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
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bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
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bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
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unsigned OpToUse = 0;
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if (HasSMUL_LOHI && !HasMULHS) {
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OpToUse = ISD::SMUL_LOHI;
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} else if (HasUMUL_LOHI && !HasMULHU) {
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OpToUse = ISD::UMUL_LOHI;
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} else if (HasSMUL_LOHI) {
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OpToUse = ISD::SMUL_LOHI;
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} else if (HasUMUL_LOHI) {
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OpToUse = ISD::UMUL_LOHI;
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}
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if (OpToUse) {
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Result = DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2);
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break;
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}
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}
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if (Node->getOpcode() == ISD::MULHS &&
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TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
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Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
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VTs, Tmp1, Tmp2).getNode(),
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1);
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break;
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}
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if (Node->getOpcode() == ISD::MULHU &&
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TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
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Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
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VTs, Tmp1, Tmp2).getNode(),
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1);
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break;
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}
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if (Node->getOpcode() == ISD::SDIV &&
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TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
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Result = DAG.getNode(ISD::SDIVREM, dl, VTs, Tmp1, Tmp2);
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break;
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}
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if (Node->getOpcode() == ISD::UDIV &&
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TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
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Result = DAG.getNode(ISD::UDIVREM, dl, VTs, Tmp1, Tmp2);
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break;
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}
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if (Node->getOpcode() == ISD::SUB &&
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TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
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TLI.isOperationLegalOrCustom(ISD::XOR, VT)) {
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Tmp2 = DAG.getNode(ISD::XOR, dl, VT, Tmp2,
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DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
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Tmp2 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
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Result = DAG.getNode(ISD::ADD, dl, VT, Tmp1, Tmp2);
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break;
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}
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// Check to see if we have a libcall for this operator.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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bool isSigned = false;
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switch (Node->getOpcode()) {
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case ISD::UDIV:
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case ISD::SDIV:
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isSigned = Node->getOpcode() == ISD::SDIV;
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if (VT == MVT::i16)
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LC = (isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16);
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else if (VT == MVT::i32)
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LC = (isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32);
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else if (VT == MVT::i64)
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LC = (isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64);
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else if (VT == MVT::i128)
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LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128);
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break;
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case ISD::MUL:
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if (VT == MVT::i16)
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LC = RTLIB::MUL_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::MUL_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::MUL_I64;
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else if (VT == MVT::i128)
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LC = RTLIB::MUL_I128;
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break;
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default: break;
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}
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if (LC != RTLIB::UNKNOWN_LIBCALL) {
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Result = ExpandLibCall(LC, Node, isSigned);
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break;
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}
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assert(0 && "Cannot expand this binary operator!");
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break;
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}
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}
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break;
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case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
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@ -3487,6 +3295,111 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
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RTLIB::REM_F80, RTLIB::REM_PPCF128));
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break;
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case ISD::EHSELECTION: {
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unsigned Reg = TLI.getExceptionSelectorRegister();
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assert(Reg && "Can't expand to unknown register!");
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Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
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Node->getValueType(0)));
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Results.push_back(Results[0].getValue(1));
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break;
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}
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case ISD::EXCEPTIONADDR: {
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unsigned Reg = TLI.getExceptionAddressRegister();
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assert(Reg && "Can't expand to unknown register!");
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Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
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Node->getValueType(0)));
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Results.push_back(Results[0].getValue(1));
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break;
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}
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case ISD::SUB: {
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MVT VT = Node->getValueType(0);
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assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
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TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
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"Don't know how to expand this subtraction!");
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Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
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DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
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Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
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Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
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break;
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}
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case ISD::UDIV:
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case ISD::UREM: {
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bool isRem = Node->getOpcode() == ISD::UREM;
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT))
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Tmp1 = DAG.getNode(ISD::UDIVREM, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)).getValue(isRem);
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else if (isRem)
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
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RTLIB::UREM_I64, RTLIB::UREM_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
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RTLIB::UDIV_I64, RTLIB::UDIV_I128);
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Results.push_back(Tmp1);
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break;
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}
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case ISD::SDIV:
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case ISD::SREM: {
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bool isRem = Node->getOpcode() == ISD::SREM;
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT))
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Tmp1 = DAG.getNode(ISD::SDIVREM, dl, VTs, Node->getOperand(0),
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Node->getOperand(1)).getValue(isRem);
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else if (isRem)
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Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
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RTLIB::SREM_I64, RTLIB::SREM_I128);
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else
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Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
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RTLIB::SDIV_I64, RTLIB::SDIV_I128);
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Results.push_back(Tmp1);
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break;
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
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ISD::SMUL_LOHI;
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
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"If this wasn't legal, it shouldn't have been created!");
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Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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Results.push_back(Tmp1.getValue(1));
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break;
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}
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case ISD::MUL: {
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MVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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// See if multiply or divide can be lowered using two-result operations.
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// We just need the low half of the multiply; try both the signed
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// and unsigned forms. If the target supports both SMUL_LOHI and
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// UMUL_LOHI, form a preference by checking which forms of plain
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// MULH it supports.
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bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
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bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
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bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
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bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
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unsigned OpToUse = 0;
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if (HasSMUL_LOHI && !HasMULHS) {
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OpToUse = ISD::SMUL_LOHI;
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} else if (HasUMUL_LOHI && !HasMULHU) {
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OpToUse = ISD::UMUL_LOHI;
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} else if (HasSMUL_LOHI) {
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OpToUse = ISD::SMUL_LOHI;
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} else if (HasUMUL_LOHI) {
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OpToUse = ISD::UMUL_LOHI;
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}
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if (OpToUse) {
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Results.push_back(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2));
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break;
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}
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Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
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RTLIB::MUL_I64, RTLIB::MUL_I128);
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Results.push_back(Tmp1);
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break;
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}
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case ISD::GLOBAL_OFFSET_TABLE:
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case ISD::GlobalAddress:
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case ISD::GlobalTLSAddress:
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