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Fix i64 returns
Generate PowerPC 'subfic' instruction when appropriate git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -488,6 +488,7 @@ static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
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if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
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break;
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case ISD::MUL:
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case ISD::SUB:
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if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
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break;
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case ISD::SETCC:
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@ -903,10 +904,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::UNDEF:
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1;
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
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return Result;
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case ISD::DYNAMIC_STACKALLOC:
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@ -1212,9 +1209,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::SUB:
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assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
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if (1 == canUseAsImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
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BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
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else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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return Result;
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case ISD::MUL:
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@ -1524,8 +1525,8 @@ void ISel::Select(SDOperand N) {
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = SelectExpr(N.getOperand(2));
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BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
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BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
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BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
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break;
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case 2:
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Select(N.getOperand(0));
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