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AArch64: Use cbnz instead of cmp/b.ne pair for atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176253 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
5e81213969
commit
279b9184c2
@ -341,8 +341,7 @@ AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// ldxr dest, ptr
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// <binop> scratch, dest, incr
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// stxr stxr_status, scratch, ptr
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// cmp stxr_status, #0
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// b.ne loopMBB
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// cbnz stxr_status, loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
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@ -364,10 +363,8 @@ AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
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BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
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BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
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.addReg(stxr_status).addImm(0);
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BuildMI(BB, dl, TII->get(AArch64::Bcc))
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.addImm(A64CC::NE).addMBB(loopMBB);
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BuildMI(BB, dl, TII->get(AArch64::CBNZw))
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.addReg(stxr_status).addMBB(loopMBB);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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@ -437,8 +434,7 @@ AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
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// cmp incr, dest (, sign extend if necessary)
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// csel scratch, dest, incr, cond
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// stxr stxr_status, scratch, ptr
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// cmp stxr_status, #0
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// b.ne loopMBB
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// cbnz stxr_status, loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
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@ -457,10 +453,8 @@ AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
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BuildMI(BB, dl, TII->get(strOpc), stxr_status)
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.addReg(scratch).addReg(ptr);
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BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
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.addReg(stxr_status).addImm(0);
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BuildMI(BB, dl, TII->get(AArch64::Bcc))
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.addImm(A64CC::NE).addMBB(loopMBB);
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BuildMI(BB, dl, TII->get(AArch64::CBNZw))
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.addReg(stxr_status).addMBB(loopMBB);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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@ -533,17 +527,14 @@ AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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// loop2MBB:
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// strex stxr_status, newval, [ptr]
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// cmp stxr_status, #0
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// b.ne loop1MBB
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// cbnz stxr_status, loop1MBB
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BB = loop2MBB;
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unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
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BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
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BuildMI(BB, dl, TII->get(AArch64::SUBwwi_lsl0_cmp))
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.addReg(stxr_status).addImm(0);
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BuildMI(BB, dl, TII->get(AArch64::Bcc))
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.addImm(A64CC::NE).addMBB(loop1MBB);
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BuildMI(BB, dl, TII->get(AArch64::CBNZw))
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.addReg(stxr_status).addMBB(loop1MBB);
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BB->addSuccessor(loop1MBB);
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BB->addSuccessor(exitMBB);
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@ -159,7 +159,7 @@ let Defs = [XSP], Uses = [XSP] in {
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// Atomic operation pseudo-instructions
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//===----------------------------------------------------------------------===//
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let usesCustomInserter = 1, Defs = [NZCV] in {
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let usesCustomInserter = 1 in {
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multiclass AtomicSizes<string opname> {
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def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
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[(set GPR32:$dst, (!cast<SDNode>(opname # "_8") GPR64:$ptr, GPR32:$incr))]>;
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@ -178,11 +178,14 @@ defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">;
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defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">;
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defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">;
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defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">;
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defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
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defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
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defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
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defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
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defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">;
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let Defs = [NZCV] in {
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// These operations need a CMP to calculate the correct value
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defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
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defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
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defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
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defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
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}
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let usesCustomInserter = 1, Defs = [NZCV] in {
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def ATOMIC_CMP_SWAP_I8
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@ -18,8 +18,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
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; function there.
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; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -39,8 +38,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
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; function there.
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; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -60,8 +58,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
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; function there.
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; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -81,8 +78,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
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; function there.
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; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -102,8 +98,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
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; function there.
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; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -123,8 +118,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
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; function there.
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; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -144,8 +138,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
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; function there.
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; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -165,8 +158,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
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; function there.
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; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -186,8 +178,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
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; function there.
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; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -207,8 +198,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
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; function there.
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; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -228,8 +218,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
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; function there.
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; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -249,8 +238,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
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; function there.
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; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -270,8 +258,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
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; function there.
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; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -291,8 +278,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
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; function there.
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; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -312,8 +298,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
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; function there.
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; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -333,8 +318,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
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; function there.
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; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -354,8 +338,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
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; function there.
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; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -375,8 +358,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
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; function there.
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; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -396,8 +378,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
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; function there.
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; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -417,8 +398,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
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; function there.
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; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -437,8 +417,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
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; w0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -457,8 +436,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
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; w0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
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@ -477,8 +455,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
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; w0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
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; CHECK: dmb ish
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; CHECK: mov x0, x[[OLD]]
|
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@ -497,8 +474,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
|
||||
; x0 below is a reasonable guess but could change: it certainly comes into the
|
||||
; function there.
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -520,8 +496,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], sxtb
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
|
||||
; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -542,8 +517,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], sxth
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
|
||||
; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -564,8 +538,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -586,8 +559,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp x0, x[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -608,8 +580,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], sxtb
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
|
||||
; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -630,8 +601,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], sxth
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
|
||||
; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -652,8 +622,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -674,8 +643,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp x0, x[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -696,8 +664,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], uxtb
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
|
||||
; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -718,8 +685,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], uxth
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
|
||||
; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -740,8 +706,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -762,8 +727,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp x0, x[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -784,8 +748,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], uxtb
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
|
||||
; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -806,8 +769,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]], uxth
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
|
||||
; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -828,8 +790,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp w0, w[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -850,8 +811,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
|
||||
; CHECK-NEXT: cmp x0, x[[OLD]]
|
||||
; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo
|
||||
; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne .LBB{{[0-9]+}}_1
|
||||
; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -873,8 +833,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
|
||||
; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
|
||||
; As above, w1 is a reasonable guess.
|
||||
; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne [[STARTAGAIN]]
|
||||
; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -896,8 +855,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
|
||||
; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
|
||||
; As above, w1 is a reasonable guess.
|
||||
; CHECK: stxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne [[STARTAGAIN]]
|
||||
; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -919,8 +877,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
|
||||
; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
|
||||
; As above, w1 is a reasonable guess.
|
||||
; CHECK: stxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne [[STARTAGAIN]]
|
||||
; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
@ -942,8 +899,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
|
||||
; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
|
||||
; As above, w1 is a reasonable guess.
|
||||
; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
|
||||
; CHECK-NEXT: cmp [[STATUS]], #0
|
||||
; CHECK-NEXT: b.ne [[STARTAGAIN]]
|
||||
; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
|
||||
; CHECK: dmb ish
|
||||
|
||||
; CHECK: mov x0, x[[OLD]]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user