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[AVR] Expand MULHS for all types

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Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.

Authored by Jake Goulding

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283634 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dylan McKay 2016-10-08 01:01:49 +00:00
parent dc87e8eb52
commit 2884d8d5ee
3 changed files with 56 additions and 0 deletions
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3
lib/Target/AVR/AVRISelLowering.h
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@ -92,6 +92,9 @@ public:
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;

31
test/CodeGen/AVR/smul-with-overflow.ll Normal file
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@ -0,0 +1,31 @@
; RUN: llc < %s -march=avr | FileCheck %s
define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: signed_multiplication_did_overflow:
entry-block:
%2 = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %0, i8 %1)
%3 = extractvalue { i8, i1 } %2, 1
ret i1 %3
; Multiply, fill the low byte with the sign of the low byte via
; arithmetic shifting, compare it to the high byte.
;
; CHECK: muls r24, r22
; CHECK: mov [[HIGH:r[0-9]+]], r1
; CHECK: mov [[LOW:r[0-9]+]], r0
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]]
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]]
; CHECK: brne [[LABEL:LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
}
declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8)

22
test/CodeGen/AVR/umul-with-overflow.ll Normal file
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@ -0,0 +1,22 @@
; RUN: llc < %s -march=avr | FileCheck %s
define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: unsigned_multiplication_did_overflow:
entry-block:
%2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1)
%3 = extractvalue { i8, i1 } %2, 1
ret i1 %3
; Multiply, return if the high byte is zero
;
; CHECK: mul r{{[0-9]+}}, r{{[0-9]+}}
; CHECK: mov [[HIGH:r[0-9]+]], r1
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cpi {{.*}}[[HIGH]], 0
; CHECK: brne [[LABEL:LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
}
declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8)