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https://github.com/RPCSX/llvm.git
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Add pseudo instructions to the XCore for (load|store|load address) of a
frame index. eliminateFrameIndex will replace these instructions with (LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use. This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame pointer elimination. However since they were marked as implicitly using SP they could not be rematerialised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
a8c78a9e89
commit
29cab5f0ee
@ -77,7 +77,7 @@ bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned
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XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::LDWSP_ru6 || Opcode == XCore::LDWSP_lru6)
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if (Opcode == XCore::LDWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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@ -99,19 +99,11 @@ unsigned
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XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::STWSP_ru6 || Opcode == XCore::STWSP_lru6)
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if (Opcode == XCore::STWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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else if (Opcode == XCore::STWSP_ru6_2 || Opcode == XCore::STWSP_lru6_2)
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{
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if (MI->getOperand(1).isFI())
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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@ -387,8 +379,8 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const
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{
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BuildMI(MBB, I, get(XCore::STWSP_lru6)).addReg(SrcReg, false, false, isKill)
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.addFrameIndex(FrameIndex).addImm(0);
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BuildMI(MBB, I, get(XCore::STWFI)).addReg(SrcReg, false, false, isKill)
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.addFrameIndex(FrameIndex).addImm(0);
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}
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void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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@ -404,8 +396,8 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const
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{
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BuildMI(MBB, I, get(XCore::LDWSP_lru6), DestReg).addFrameIndex(FrameIndex)
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.addImm(0);
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BuildMI(MBB, I, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex)
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.addImm(0);
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}
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void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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@ -349,6 +349,18 @@ def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
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"${:comment} LDWFI $dst, $addr",
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[(set GRRegs:$dst, (load ADDRspii:$addr))]>;
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def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
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"${:comment} LDAWFI $dst, $addr",
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[(set GRRegs:$dst, ADDRspii:$addr)]>;
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def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
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"${:comment} STWFI $src, $addr",
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[(store GRRegs:$src, ADDRspii:$addr)]>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1 in {
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@ -543,51 +555,41 @@ let mayLoad = 1, isReMaterializable = 1 in
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defm LDWCP : FRU6_LRU6_cp<"ldw">;
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let Uses = [SP] in {
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let mayStore=1 in
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let mayStore=1 in {
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def STWSP_ru6 : _FRU6<
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(outs), (ins GRRegs:$dst, MEMii:$b),
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"stw $dst, sp[$b]",
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[]>;
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(outs), (ins GRRegs:$val, i32imm:$index),
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"stw $val, sp[$index]",
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[(XCoreStwsp GRRegs:$val, immU6:$index)]>;
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def STWSP_lru6 : _FLRU6<
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(outs), (ins GRRegs:$dst, MEMii:$b),
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"stw $dst, sp[$b]",
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[(store GRRegs:$dst, ADDRspii:$b)]>;
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(outs), (ins GRRegs:$val, i32imm:$index),
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"stw $val, sp[$index]",
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[(XCoreStwsp GRRegs:$val, immU16:$index)]>;
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}
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let mayStore=1 in
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def STWSP_ru6_2 : _FRU6<
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(outs), (ins GRRegs:$dst, i32imm:$b),
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"stw $dst, sp[$b]",
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[]>;
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def STWSP_lru6_2 : _FLRU6<
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(outs), (ins GRRegs:$dst, i32imm:$b),
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"stw $dst, sp[$b]",
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[(store GRRegs:$dst, ADDRspii:$b)]>;
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let mayLoad=1 in
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let mayLoad=1 in {
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def LDWSP_ru6 : _FRU6<
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(outs GRRegs:$dst), (ins MEMii:$b),
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldw $dst, sp[$b]",
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[]>;
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def LDWSP_lru6 : _FLRU6<
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(outs GRRegs:$dst), (ins MEMii:$b),
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldw $dst, sp[$b]",
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[(set GRRegs:$dst, (load ADDRspii:$b))]>;
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[]>;
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}
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let neverHasSideEffects = 1 in
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let neverHasSideEffects = 1 in {
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def LDAWSP_ru6 : _FRU6<
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(outs GRRegs:$dst), (ins MEMii:$b),
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[]>;
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def LDAWSP_lru6 : _FLRU6<
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(outs GRRegs:$dst), (ins MEMii:$b),
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[(set GRRegs: $dst, ADDRspii:$b)]>;
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[]>;
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let neverHasSideEffects = 1 in {
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def LDAWSP_ru6_RRegs : _FRU6<
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(outs RRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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@ -808,10 +810,6 @@ def GETID_0R : _F0R<(outs), (ins),
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def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
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def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
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def : Pat<(XCoreStwsp GRRegs:$val, immU6:$index),
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(STWSP_ru6_2 GRRegs:$val, immU6:$index)>;
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def : Pat<(XCoreStwsp GRRegs:$val, immU16:$index),
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(STWSP_lru6_2 GRRegs:$val, immU16:$index)>;
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/// sext_inreg
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def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
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@ -211,19 +211,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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bool FP = hasFP(MF);
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unsigned Reg = MI.getOperand(0).getReg();
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bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
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assert(XCore::GRRegsRegisterClass->contains(Reg) &&
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"Unexpected register operand");
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MachineBasicBlock &MBB = *MI.getParent();
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if (FP) {
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bool isUs = isImmUs(Offset);
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MachineBasicBlock &MBB = *MI.getParent();
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unsigned FramePtr = XCore::R10;
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unsigned Reg = MI.getOperand(0).getReg();
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bool isKill = MI.getOperand(0).isKill();
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if (Reg == XCore::LR) {
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// The LR should have been save in the prologue.
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cerr << "saving LR to FP unimplemented\n";
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abort();
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}
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MachineInstr *New = 0;
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if (!isUs) {
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if (!RS) {
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@ -234,18 +233,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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SPAdj);
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loadConstant(MBB, II, ScratchReg, Offset);
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switch (MI.getOpcode()) {
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case XCore::LDWSP_lru6:
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case XCore::LDWFI:
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New = BuildMI(MBB, II, TII.get(XCore::LDW_3r), Reg)
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.addReg(FramePtr)
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.addReg(ScratchReg, false, false, true);
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break;
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case XCore::STWSP_lru6:
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case XCore::STWFI:
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New = BuildMI(MBB, II, TII.get(XCore::STW_3r))
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.addReg(Reg, false, false, isKill)
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.addReg(FramePtr)
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.addReg(ScratchReg, false, false, true);
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break;
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case XCore::LDAWSP_lru6:
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case XCore::LDAWFI:
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New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l3r), Reg)
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.addReg(FramePtr)
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.addReg(ScratchReg, false, false, true);
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@ -255,18 +254,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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}
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} else {
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switch (MI.getOpcode()) {
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case XCore::LDWSP_lru6:
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case XCore::LDWFI:
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New = BuildMI(MBB, II, TII.get(XCore::LDW_2rus), Reg)
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.addReg(FramePtr)
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.addImm(Offset);
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break;
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case XCore::STWSP_lru6:
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case XCore::STWFI:
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New = BuildMI(MBB, II, TII.get(XCore::STW_2rus))
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.addReg(Reg, false, false, isKill)
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.addReg(FramePtr)
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.addImm(Offset);
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break;
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case XCore::LDAWSP_lru6:
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case XCore::LDAWFI:
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New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l2rus), Reg)
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.addReg(FramePtr)
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.addImm(Offset);
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@ -275,9 +274,6 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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assert(0 && "Unexpected Opcode\n");
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}
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}
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// Erase old instruction.
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MBB.erase(II);
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} else {
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset)) {
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@ -286,25 +282,30 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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abort();
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}
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int NewOpcode = MI.getOpcode();
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switch (NewOpcode) {
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case XCore::LDWSP_lru6:
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switch (MI.getOpcode()) {
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int NewOpcode;
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case XCore::LDWFI:
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NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, II, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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break;
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case XCore::STWSP_lru6:
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case XCore::STWFI:
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NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, II, TII.get(NewOpcode))
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.addReg(Reg, false, false, isKill)
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.addImm(Offset);
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break;
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case XCore::LDAWSP_lru6:
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case XCore::LDAWFI:
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NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, II, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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break;
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default:
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assert(0 && "Unexpected Opcode\n");
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}
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MI.setDesc(TII.get(NewOpcode));
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FrameOp.ChangeToImmediate(Offset);
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}
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// Erase old instruction.
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MBB.erase(II);
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}
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void
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@ -372,8 +373,7 @@ storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, I, TII.get(Opcode))
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.addReg(SrcReg)
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.addImm(Offset)
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.addImm(0);
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.addImm(Offset);
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}
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void XCoreRegisterInfo::
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@ -388,8 +388,7 @@ loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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}
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int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, I, TII.get(Opcode), DstReg)
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.addImm(Offset)
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.addImm(0);
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.addImm(Offset);
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}
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void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
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18
test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
Normal file
18
test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llvm-as < %s | llc -march=xcore > %t1.s
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; PR3324
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define double @f1(double %a, double %b, double %c, double %d, double %e, double %f, double %g) nounwind {
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entry:
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br i1 false, label %bb113, label %bb129
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bb113: ; preds = %entry
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ret double 0.000000e+00
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bb129: ; preds = %entry
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%tmp134 = sub double %b, %a ; <double> [#uses=1]
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%tmp136 = sub double %tmp134, %c ; <double> [#uses=1]
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%tmp138 = add double %tmp136, %d ; <double> [#uses=1]
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%tmp140 = sub double %tmp138, %e ; <double> [#uses=1]
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%tmp142 = add double %tmp140, %f ; <double> [#uses=1]
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%tmp.0 = mul double %tmp142, 0.000000e+00 ; <double> [#uses=1]
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ret double %tmp.0
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}
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