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Remove extra \n from LLVM_UNREACHABLE calls.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75416 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Torok Edwin 2009-07-12 07:15:17 +00:00
parent 7ab2eb4a80
commit 29fd056d81
9 changed files with 16 additions and 17 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -594,7 +594,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
// We allow inline assembler nodes with empty bodies - they can // We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT. // implicitly define registers, which is ok for JIT.
if (MI.getOperand(0).getSymbolName()[0]) { if (MI.getOperand(0).getSymbolName()[0]) {
llvm_report_error("JIT does not support inline asm!\n"); llvm_report_error("JIT does not support inline asm!");
} }
break; break;
} }

2
lib/Target/ARM/ARMJITInfo.cpp
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@ -104,7 +104,7 @@ extern "C" {
); );
#else // Not an ARM host #else // Not an ARM host
void ARMCompilationCallback() { void ARMCompilationCallback() {
LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n"); LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
} }
#endif #endif
} }

4
lib/Target/IA64/IA64ISelLowering.cpp
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@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
switch (getValueType(I->getType()).getSimpleVT()) { switch (getValueType(I->getType()).getSimpleVT()) {
default: default:
LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.\n"); LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32: case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff, // fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs) // see intel ABI docs)
@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
if (InFlag.getNode()) if (InFlag.getNode())
CallOperands.push_back(InFlag); CallOperands.push_back(InFlag);
else else
LLVM_UNREACHABLE("this should never happen!\n"); LLVM_UNREACHABLE("this should never happen!");
// to make way for a hack: // to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys, Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,

7
lib/Target/IA64/IA64InstrInfo.cpp
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@ -129,8 +129,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
} else if (RC == IA64::PRRegisterClass) { } else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1; Opc = IA64::ST1;
} else { } else {
LLVM_UNREACHABLE( LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
"sorry, I don't know how to store this sort of reg\n");
} }
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
@ -165,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addReg(IA64::r0); .addReg(IA64::r0);
} else { } else {
LLVM_UNREACHABLE( LLVM_UNREACHABLE(
"sorry, I don't know how to load this sort of reg from the stack\n"); "sorry, I don't know how to load this sort of reg from the stack");
} }
} }
@ -182,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Opc = IA64::LD1; Opc = IA64::LD1;
} else { } else {
LLVM_UNREACHABLE( LLVM_UNREACHABLE(
"sorry, I don't know how to load this sort of reg\n"); "sorry, I don't know how to load this sort of reg");
} }
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();

2
lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
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@ -55,7 +55,7 @@ void X86ATTAsmPrinter::PrintPICBaseSymbol() const {
else if (Subtarget->isTargetELF()) else if (Subtarget->isTargetELF())
O << ".Lllvm$" << getFunctionNumber() << ".$piclabel"; O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
else else
LLVM_UNREACHABLE( "Don't know how to print PIC label!\n"); LLVM_UNREACHABLE( "Don't know how to print PIC label!");
} }
/// PrintUnmangledNameSafely - Print out the printable characters in the name. /// PrintUnmangledNameSafely - Print out the printable characters in the name.

4
lib/Target/X86/X86JITInfo.cpp
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@ -322,7 +322,7 @@ extern "C" {
#else // Not an i386 host #else // Not an i386 host
void X86CompilationCallback() { void X86CompilationCallback() {
LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n"); LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
} }
#endif #endif
} }
@ -554,7 +554,7 @@ char* X86JITInfo::allocateThreadLocalMemory(size_t size) {
TLSOffset -= size; TLSOffset -= size;
return TLSOffset; return TLSOffset;
#else #else
LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!\n"); LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
return 0; return 0;
#endif #endif
} }

4
lib/Target/XCore/XCoreInstrInfo.cpp
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@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const SmallVectorImpl<MachineInstr*> &NewMIs) const
{ {
LLVM_UNREACHABLE("unimplemented\n"); LLVM_UNREACHABLE("unimplemented");
} }
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const SmallVectorImpl<MachineInstr*> &NewMIs) const
{ {
LLVM_UNREACHABLE("unimplemented\n"); LLVM_UNREACHABLE("unimplemented");
} }
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,

6
lib/Target/XCore/XCoreRegisterInfo.cpp
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@ -257,7 +257,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
.addReg(ScratchReg, RegState::Kill); .addReg(ScratchReg, RegState::Kill);
break; break;
default: default:
LLVM_UNREACHABLE("Unexpected Opcode\n"); LLVM_UNREACHABLE("Unexpected Opcode");
} }
} else { } else {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
@ -278,7 +278,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
.addImm(Offset); .addImm(Offset);
break; break;
default: default:
LLVM_UNREACHABLE("Unexpected Opcode\n"); LLVM_UNREACHABLE("Unexpected Opcode");
} }
} }
} else { } else {
@ -309,7 +309,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
.addImm(Offset); .addImm(Offset);
break; break;
default: default:
LLVM_UNREACHABLE("Unexpected Opcode\n"); LLVM_UNREACHABLE("Unexpected Opcode");
} }
} }
// Erase old instruction. // Erase old instruction.

2
lib/VMCore/Constants.cpp
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@ -1121,7 +1121,7 @@ namespace llvm {
template<class ConstantClass, class TypeClass> template<class ConstantClass, class TypeClass>
struct VISIBILITY_HIDDEN ConvertConstantType { struct VISIBILITY_HIDDEN ConvertConstantType {
static void convert(ConstantClass *OldC, const TypeClass *NewTy) { static void convert(ConstantClass *OldC, const TypeClass *NewTy) {
LLVM_UNREACHABLE("This type cannot be converted!\n"); LLVM_UNREACHABLE("This type cannot be converted!");
} }
}; };