RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 20:59:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600/SI: Add processor types for each SI variant

Browse Source 
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-04-05 23:31:35 +00:00
parent 2fc7443498
commit 2a4d3e7e87
10 changed files with 16 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/R600/AMDILDeviceInfo.cpp
View File

@ -79,7 +79,9 @@ AMDGPUDevice* getDeviceFromName(const std::string &deviceName,
" on 32bit pointers!");
#endif
return new AMDGPUNIDevice(ptr);
} else if (deviceName == "SI") {
} else if (deviceName == "SI" ||
deviceName == "tahiti" || deviceName == "pitcairn" ||
deviceName == "verde" || deviceName == "oland") {
return new AMDGPUSIDevice(ptr);
} else {
#if DEBUG

7
lib/Target/R600/Processors.td
View File

@ -26,5 +26,8 @@ def : Proc<"barts", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"turks", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"caicos", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"cayman", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>;
def : Proc<"SI", SI_Itin, [Feature64BitPtr]>;
def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>;

2
test/CodeGen/R600/imm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
; XXX: Enable once SI supports buffer stores
; XFAIL: *

2
test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: S_MOV_B32
;CHECK-NEXT: V_INTERP_MOV_F32

2
test/CodeGen/R600/llvm.SI.sample.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE

2
test/CodeGen/R600/lshl.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0

2
test/CodeGen/R600/lshr.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0

2
test/CodeGen/R600/mulhu.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_MOV_B32_e32 VGPR1, -1431655765
;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0

2
test/CodeGen/R600/seto.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0

2
test/CodeGen/R600/setuo.ll
View File

@ -1,4 +1,4 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0