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Tidy up. Better base class factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -498,31 +498,23 @@ defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
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def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
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class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
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InstrItinClass itin>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
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(ins addrmode6:$Rn), IIC_VLD2,
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"vld2", Dt, "$Vd, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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class VLD2Q<bits<4> op7_4, string Dt, RegisterOperand VdTy>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs VdTy:$Vd),
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(ins addrmode6:$Rn), IIC_VLD2x2,
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(ins addrmode6:$Rn), itin,
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"vld2", Dt, "$Vd, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
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def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
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def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
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def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
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def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
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def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
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def VLD2q8 : VLD2Q<{0,0,?,?}, "8", VecListFourD>;
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def VLD2q16 : VLD2Q<{0,1,?,?}, "16", VecListFourD>;
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def VLD2q32 : VLD2Q<{1,0,?,?}, "32", VecListFourD>;
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def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
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def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
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def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
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def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
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@ -534,7 +526,7 @@ def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
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// ...with address register writeback:
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class VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
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InstrItinClass itin>
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InstrItinClass itin>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), itin,
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"vld2", Dt, "$Vd, $Rn$Rm",
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@ -560,9 +552,9 @@ def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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// ...with double-spaced registers
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def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
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def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
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def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
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def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
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def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
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def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
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def VLD2b8_UPD : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
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def VLD2b16_UPD : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
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def VLD2b32_UPD : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
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