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X86: peephole optimization to remove cmp instruction
For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
parent
fd065bbed1
commit
2af66dc51a
@ -1143,7 +1143,9 @@ let Uses = [EFLAGS] in {
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0, 0>;
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0, 0>;
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}
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}
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let isCompare = 1 in {
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defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
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defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -2865,6 +2865,291 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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NewMIs.push_back(MIB);
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NewMIs.push_back(MIB);
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}
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}
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bool X86InstrInfo::
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analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
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int &CmpMask, int &CmpValue) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP8ri:
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SrcReg = MI->getOperand(0).getReg();
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SrcReg2 = 0;
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CmpMask = ~0;
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CmpValue = MI->getOperand(1).getImm();
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return true;
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case X86::CMP64rr:
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case X86::CMP32rr:
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case X86::CMP16rr:
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case X86::CMP8rr:
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SrcReg = MI->getOperand(0).getReg();
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SrcReg2 = MI->getOperand(1).getReg();
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CmpMask = ~0;
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CmpValue = 0;
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return true;
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}
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return false;
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}
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/// getSwappedConditionForSET - assume the flags are set by MI(a,b), return
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/// the opcode if we modify the instructions such that flags are
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/// set by MI(b,a).
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static unsigned getSwappedConditionForSET(unsigned SETOpc) {
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switch (SETOpc) {
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default: return 0;
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case X86::SETEr: return X86::SETEr;
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case X86::SETEm: return X86::SETEm;
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case X86::SETNEr: return X86::SETNEr;
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case X86::SETNEm: return X86::SETNEm;
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case X86::SETLr: return X86::SETGr;
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case X86::SETLm: return X86::SETGm;
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case X86::SETLEr: return X86::SETGEr;
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case X86::SETLEm: return X86::SETGEm;
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case X86::SETGr: return X86::SETLr;
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case X86::SETGm: return X86::SETLm;
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case X86::SETGEr: return X86::SETLEr;
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case X86::SETGEm: return X86::SETLEm;
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case X86::SETBr: return X86::SETAr;
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case X86::SETBm: return X86::SETAm;
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case X86::SETBEr: return X86::SETAEr;
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case X86::SETBEm: return X86::SETAEm;
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case X86::SETAr: return X86::SETBr;
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case X86::SETAm: return X86::SETBm;
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case X86::SETAEr: return X86::SETBEr;
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case X86::SETAEm: return X86::SETBEm;
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}
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}
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/// getSwappedConditionForBranch - assume the flags are set by MI(a,b), return
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/// the opcode if we modify the instructions such that flags are
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/// set by MI(b,a).
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static unsigned getSwappedConditionForBranch(unsigned BranchOpc) {
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switch (BranchOpc) {
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default: return 0;
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case X86::JE_4: return X86::JE_4;
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case X86::JNE_4: return X86::JNE_4;
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case X86::JL_4: return X86::JG_4;
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case X86::JLE_4: return X86::JGE_4;
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case X86::JG_4: return X86::JL_4;
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case X86::JGE_4: return X86::JLE_4;
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case X86::JB_4: return X86::JA_4;
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case X86::JBE_4: return X86::JAE_4;
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case X86::JA_4: return X86::JB_4;
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case X86::JAE_4: return X86::JBE_4;
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}
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}
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/// getSwappedConditionForCMov - assume the flags are set by MI(a,b), return
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/// the opcode if we modify the instructions such that flags are
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/// set by MI(b,a).
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static unsigned getSwappedConditionForCMov(unsigned CMovOpc) {
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switch (CMovOpc) {
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default: return 0;
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case X86::CMOVE16rm: return X86::CMOVE16rm;
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case X86::CMOVE16rr: return X86::CMOVE16rr;
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case X86::CMOVE32rm: return X86::CMOVE32rm;
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case X86::CMOVE32rr: return X86::CMOVE32rr;
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case X86::CMOVE64rm: return X86::CMOVE64rm;
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case X86::CMOVE64rr: return X86::CMOVE64rr;
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case X86::CMOVNE16rm: return X86::CMOVNE16rm;
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case X86::CMOVNE16rr: return X86::CMOVNE16rr;
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case X86::CMOVNE32rm: return X86::CMOVNE32rm;
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case X86::CMOVNE32rr: return X86::CMOVNE32rr;
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case X86::CMOVNE64rm: return X86::CMOVNE64rm;
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case X86::CMOVNE64rr: return X86::CMOVNE64rr;
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case X86::CMOVL16rm: return X86::CMOVG16rm;
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case X86::CMOVL16rr: return X86::CMOVG16rr;
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case X86::CMOVL32rm: return X86::CMOVG32rm;
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case X86::CMOVL32rr: return X86::CMOVG32rr;
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case X86::CMOVL64rm: return X86::CMOVG64rm;
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case X86::CMOVL64rr: return X86::CMOVG64rr;
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case X86::CMOVLE16rm: return X86::CMOVGE16rm;
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case X86::CMOVLE16rr: return X86::CMOVGE16rr;
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case X86::CMOVLE32rm: return X86::CMOVGE32rm;
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case X86::CMOVLE32rr: return X86::CMOVGE32rr;
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case X86::CMOVLE64rm: return X86::CMOVGE64rm;
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case X86::CMOVLE64rr: return X86::CMOVGE64rr;
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case X86::CMOVG16rm: return X86::CMOVL16rm;
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case X86::CMOVG16rr: return X86::CMOVL16rr;
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case X86::CMOVG32rm: return X86::CMOVL32rm;
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case X86::CMOVG32rr: return X86::CMOVL32rr;
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case X86::CMOVG64rm: return X86::CMOVL64rm;
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case X86::CMOVG64rr: return X86::CMOVL64rr;
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case X86::CMOVGE16rm: return X86::CMOVLE16rm;
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case X86::CMOVGE16rr: return X86::CMOVLE16rr;
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case X86::CMOVGE32rm: return X86::CMOVLE32rm;
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case X86::CMOVGE32rr: return X86::CMOVLE32rr;
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case X86::CMOVGE64rm: return X86::CMOVLE64rm;
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case X86::CMOVGE64rr: return X86::CMOVLE64rr;
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case X86::CMOVB16rm: return X86::CMOVA16rm;
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case X86::CMOVB16rr: return X86::CMOVA16rr;
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case X86::CMOVB32rm: return X86::CMOVA32rm;
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case X86::CMOVB32rr: return X86::CMOVA32rr;
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case X86::CMOVB64rm: return X86::CMOVA64rm;
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case X86::CMOVB64rr: return X86::CMOVA64rr;
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case X86::CMOVBE16rm: return X86::CMOVAE16rm;
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case X86::CMOVBE16rr: return X86::CMOVAE16rr;
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case X86::CMOVBE32rm: return X86::CMOVAE32rm;
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case X86::CMOVBE32rr: return X86::CMOVAE32rr;
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case X86::CMOVBE64rm: return X86::CMOVAE64rm;
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case X86::CMOVBE64rr: return X86::CMOVAE64rr;
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case X86::CMOVA16rm: return X86::CMOVB16rm;
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case X86::CMOVA16rr: return X86::CMOVB16rr;
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case X86::CMOVA32rm: return X86::CMOVB32rm;
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case X86::CMOVA32rr: return X86::CMOVB32rr;
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case X86::CMOVA64rm: return X86::CMOVB64rm;
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case X86::CMOVA64rr: return X86::CMOVB64rr;
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case X86::CMOVAE16rm: return X86::CMOVBE16rm;
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case X86::CMOVAE16rr: return X86::CMOVBE16rr;
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case X86::CMOVAE32rm: return X86::CMOVBE32rm;
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case X86::CMOVAE32rr: return X86::CMOVBE32rr;
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case X86::CMOVAE64rm: return X86::CMOVBE64rm;
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case X86::CMOVAE64rr: return X86::CMOVBE64rr;
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}
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}
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/// isRedundantFlagInstr - check whether the first instruction, whose only
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/// purpose is to update flags, can be made redundant.
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/// CMPrr can be made redundant by SUBrr if the operands are the same.
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/// This function can be extended later on.
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/// SrcReg, SrcRegs: register operands for FlagI.
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/// ImmValue: immediate for FlagI if it takes an immediate.
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inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
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unsigned SrcReg2, int ImmValue,
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MachineInstr *OI) {
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if (((FlagI->getOpcode() == X86::CMP64rr &&
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OI->getOpcode() == X86::SUB64rr) ||
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(FlagI->getOpcode() == X86::CMP32rr &&
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OI->getOpcode() == X86::SUB32rr)||
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(FlagI->getOpcode() == X86::CMP16rr &&
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OI->getOpcode() == X86::SUB16rr)||
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(FlagI->getOpcode() == X86::CMP8rr &&
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OI->getOpcode() == X86::SUB8rr)) &&
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((OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getReg() == SrcReg2) ||
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(OI->getOperand(1).getReg() == SrcReg2 &&
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OI->getOperand(2).getReg() == SrcReg)))
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return true;
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if (((FlagI->getOpcode() == X86::CMP64ri32 &&
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OI->getOpcode() == X86::SUB64ri32) ||
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(FlagI->getOpcode() == X86::CMP64ri8 &&
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OI->getOpcode() == X86::SUB64ri8) ||
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(FlagI->getOpcode() == X86::CMP32ri &&
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OI->getOpcode() == X86::SUB32ri) ||
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(FlagI->getOpcode() == X86::CMP32ri8 &&
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OI->getOpcode() == X86::SUB32ri8) ||
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(FlagI->getOpcode() == X86::CMP16ri &&
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OI->getOpcode() == X86::SUB16ri) ||
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(FlagI->getOpcode() == X86::CMP16ri8 &&
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OI->getOpcode() == X86::SUB16ri8) ||
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(FlagI->getOpcode() == X86::CMP8ri &&
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OI->getOpcode() == X86::SUB8ri)) &&
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OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getImm() == ImmValue)
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return true;
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return false;
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}
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/// optimizeCompareInstr - Check if there exists an earlier instruction that
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/// operates on the same source operands and sets flags in the same way as
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/// Compare; remove Compare if possible.
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bool X86InstrInfo::
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optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const {
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// Get the unique definition of SrcReg.
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MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
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if (!MI) return false;
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// CmpInstr is the first instruction of the BB.
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MachineBasicBlock::iterator I = CmpInstr, Def = MI;
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// We are searching for an earlier instruction that can make CmpInstr
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// redundant and that instruction will be saved in Sub.
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MachineInstr *Sub = NULL;
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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// We iterate backward, starting from the instruction before CmpInstr and
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// stop when reaching the definition of a source register or done with the BB.
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// RI points to the instruction before CmpInstr.
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// If the definition is in this basic block, RE points to the definition;
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// otherwise, RE is the rend of the basic block.
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MachineBasicBlock::reverse_iterator
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RI = MachineBasicBlock::reverse_iterator(I),
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RE = CmpInstr->getParent() == MI->getParent() ?
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MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
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CmpInstr->getParent()->rend();
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for (; RI != RE; ++RI) {
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MachineInstr *Instr = &*RI;
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// Check whether CmpInstr can be made redundant by the current instruction.
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if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
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Sub = Instr;
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break;
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}
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if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
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Instr->readsRegister(X86::EFLAGS, TRI))
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// This instruction modifies or uses EFLAGS.
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// We can't remove CmpInstr.
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return false;
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}
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// Return false if no candidates exist.
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if (!Sub)
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return false;
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// Scan forward from the instruction after CmpInstr for uses of EFLAGS.
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SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
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MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
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for (++I; I != E; ++I) {
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const MachineInstr &Instr = *I;
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if (Instr.modifiesRegister(X86::EFLAGS, TRI))
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// It is safe to remove CmpInstr if EFLAGS is updated again.
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break;
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if (!Instr.readsRegister(X86::EFLAGS, TRI))
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continue;
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// EFLAGS is used by this instruction.
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if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg) {
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// If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
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// to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
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unsigned NewOpc = getSwappedConditionForSET(Instr.getOpcode());
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if (!NewOpc) NewOpc = getSwappedConditionForBranch(Instr.getOpcode());
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if (!NewOpc) NewOpc = getSwappedConditionForCMov(Instr.getOpcode());
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if (!NewOpc) return false;
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// Push the MachineInstr to OpsToUpdate.
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// If it is safe to remove CmpInstr, the condition code of these
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// instructions will be modified.
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OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
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}
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}
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// Make sure Sub instruction defines EFLAGS.
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assert(Sub->getNumOperands() >= 4 && Sub->getOperand(3).isReg() &&
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Sub->getOperand(3).getReg() == X86::EFLAGS &&
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"EFLAGS should be the 4th operand of SUBrr or SUBri.");
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Sub->getOperand(3).setIsDef(true);
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CmpInstr->eraseFromParent();
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// Modify the condition code of instructions in OpsToUpdate.
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for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
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OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
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return true;
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}
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/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
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/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
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/// instruction with two undef reads of the register being defined. This is
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/// instruction with two undef reads of the register being defined. This is
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/// used for mapping:
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/// used for mapping:
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@ -372,6 +372,21 @@ public:
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
|
const MachineInstr *UseMI, unsigned UseIdx) const;
|
||||||
|
|
||||||
|
/// analyzeCompare - For a comparison instruction, return the source registers
|
||||||
|
/// in SrcReg and SrcReg2 if having two register operands, and the value it
|
||||||
|
/// compares against in CmpValue. Return true if the comparison instruction
|
||||||
|
/// can be analyzed.
|
||||||
|
virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
|
||||||
|
unsigned &SrcReg2,
|
||||||
|
int &CmpMask, int &CmpValue) const;
|
||||||
|
|
||||||
|
/// optimizeCompareInstr - Check if there exists an earlier instruction that
|
||||||
|
/// operates on the same source operands and sets flags in the same way as
|
||||||
|
/// Compare; remove Compare if possible.
|
||||||
|
virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
|
||||||
|
unsigned SrcReg2, int CmpMask, int CmpValue,
|
||||||
|
const MachineRegisterInfo *MRI) const;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
|
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
|
||||||
MachineFunction::iterator &MFI,
|
MachineFunction::iterator &MFI,
|
||||||
|
|||||||
@ -83,6 +83,25 @@ entry:
|
|||||||
%cond = select i1 %cmp, i32 %sub, i32 0
|
%cond = select i1 %cmp, i32 %sub, i32 0
|
||||||
ret i32 %cond
|
ret i32 %cond
|
||||||
}
|
}
|
||||||
|
; redundant cmp instruction
|
||||||
|
define i32 @l(i32 %a, i32 %b) nounwind {
|
||||||
|
entry:
|
||||||
|
; CHECK: l:
|
||||||
|
; CHECK-NOT: cmp
|
||||||
|
%cmp = icmp slt i32 %b, %a
|
||||||
|
%sub = sub nsw i32 %a, %b
|
||||||
|
%cond = select i1 %cmp, i32 %sub, i32 %a
|
||||||
|
ret i32 %cond
|
||||||
|
}
|
||||||
|
define i32 @m(i32 %a, i32 %b) nounwind {
|
||||||
|
entry:
|
||||||
|
; CHECK: m:
|
||||||
|
; CHECK-NOT: cmp
|
||||||
|
%cmp = icmp sgt i32 %a, %b
|
||||||
|
%sub = sub nsw i32 %a, %b
|
||||||
|
%cond = select i1 %cmp, i32 %b, i32 %sub
|
||||||
|
ret i32 %cond
|
||||||
|
}
|
||||||
; rdar://11540023
|
; rdar://11540023
|
||||||
define i32 @n(i32 %x, i32 %y) nounwind {
|
define i32 @n(i32 %x, i32 %y) nounwind {
|
||||||
entry:
|
entry:
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user