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This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included.

Browse Source 
Differential Review: https://reviews.llvm.org/D24660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283727 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Dewhurst 2016-10-10 08:53:06 +00:00
parent a56b5b5487
commit 2bf22e30a5
6 changed files with 29 additions and 1 deletions
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8
lib/Target/Sparc/LeonFeatures.td
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@ -37,6 +37,14 @@ def LeonCASA : SubtargetFeature<
"Enable CASA instruction for LEON3 and LEON4 processors"
>;
def ReplaceSDIV : SubtargetFeature<
"replacesdiv",
"PerformSDIVReplace",
"true",
"AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead"
>;
def InsertNOPLoad: SubtargetFeature<
"insertnopload",
"InsertNOPLoad",

2
lib/Target/Sparc/Sparc.td
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@ -110,7 +110,7 @@ def : Processor<"leon2", LEON2Itineraries,
// LEON 2 FT (AT697E)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"at697e", LEON2Itineraries,
[FeatureLeon, InsertNOPLoad]>;
[FeatureLeon, ReplaceSDIV, InsertNOPLoad]>;
// LEON 2 FT (AT697F)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.

6
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -360,6 +360,12 @@ void SparcDAGToDAGISel::Select(SDNode *N) {
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
// SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
&&
Opcode == SP::SDIVrr) {
Opcode = SP::SDIVCCrr;
}
CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
return;
}

1
lib/Target/Sparc/SparcSubtarget.cpp
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@ -39,6 +39,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
// Leon features
HasLeonCasa = false;
HasUmacSmac = false;
PerformSDIVReplace = false;
InsertNOPLoad = false;
FixFSMULD = false;
ReplaceFMULS = false;

2
lib/Target/Sparc/SparcSubtarget.h
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@ -48,6 +48,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
bool FixFSMULD;
bool ReplaceFMULS;
bool FixAllFDIVSQRT;
bool PerformSDIVReplace;
SparcInstrInfo InstrInfo;
SparcTargetLowering TLInfo;
@ -86,6 +87,7 @@ public:
// Leon options
bool hasUmacSmac() const { return HasUmacSmac; }
bool performSDIVReplace() const { return PerformSDIVReplace; }
bool hasLeonCasa() const { return HasLeonCasa; }
bool insertNOPLoad() const { return InsertNOPLoad; }
bool fixFSMULD() const { return FixFSMULD; }

11
test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc %s -O0 -march=sparc -o - | FileCheck %s -check-prefix=NO_REPLACE_SDIV
; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s -check-prefix=REPLACE_SDIV
; REPLACE_SDIV: sdivcc %o0, %o1, %o0
; NO_REPLACE_SDIV: sdiv %o0, %o1, %o0
define i32 @lbr59(i32 %a, i32 %b)
{
%r = sdiv i32 %a, %b
ret i32 %r
}